4.2 D ATA L INK ERROR RESILIENCE FOR PERMANENT FAULTS
4.2.3 Interconnect Built-In Self-Test, Self-Repair and Adaptive Serialization
number of functional groups gmin, the algorithm in Figure IV-19 determines the partitioning such that the CSL area is minimal and the target yield is achieved.
01: for g=1…gmin
02: [n1,…,ng] 31n/g2; 03: [r1,…,rg] = 0;
04: Y = YTSV n; 05: while (Y < YT)
06: i = ((i+1) mod g) + 1;
07: ri = ri + 1;
08: Y =Yield(g, gmin, n1, r1,…, ng, rg);
09: end;
10: area = estimate_area(n1,…,ng; r1,…,rg);
11: if (area < smallest_area) then 12: store(n1,…,ng; r1,…,rg);
13: end;
14: end;
Figure IV-19 Area optimization process for CSLs
Starting with one group, the regular TSV are split in quasi-equal groups, since a uniform fault distribution is considered. In lines 05-09, spares are allocated for each group n1,…,ng until the reliability target is achieved.
The interconnect yield is estimated for each group, assuming that at least gmin groups are functional. For the uncorrelated fault model, a formula for the Yield function in line 08 can be found in Chapter 5 (i.e. Equations V-4, V-5). For each group configuration, the CSL configuration area is estimated and, if this area is smaller, it is stored. At the end of this process, the CSL configuration with the smallest area is returned.
Upstream Reconfiguration Logic Downstream Reconfiguration Logic Repair
Logic
Repair Logic Diagnosis
Vector
Diagnosis Vector
… W1
W2
Wn
Wn+1
Wn+r
…
TSV Interconnect BIST TSV Interconnect BIST
DTRANS
n-bits Deserialization Logic
n-bits Serialization Logic
Xn … X3 X2 X1
Xn … X3 X2 X1
Figure IV-20 Self-repair and adaptive serial link
The self-repair and serialization/deserialization signals have to be generated on both sides of the inter-die link. Therefore, after TSV interconnect tests, the diagnosis vector DV must be stored on both sides of the link.
As mentioned in Chapter 3, the diagnosis vector DV1-DVn+r is stored in the response analysis flip-flops FF1- FFn+r (upper die in Figure IV-20). From these FFs, the diagnosis vector is serially transmitted through DTRANS
into the lower-die register. This operation is done by configuring the upstream DV register as a feed-back shift register and the downstream register as a shift register. Thus, n+r cycles after the interconnect tests, DV1- DVn+r is stored in both layers where it is further used to determine the IBIRAS repair signals.
The parameters of the design are the number of data bits n, the number of spare TSVs r, and the minimum acceptable number of fault-free TSVs mLIMIT which determines the maximum acceptable number of serialization cycles KMAX. If the number of fault-free TSVs is less than mLIMIT then the link is assumed failed.
The interconnect test diagnosis vector DV obtained in the test phase is used to determine the IBIRAS self- repair and adaptive serialization control signals. The upstream and downstream Reconfiguration Logic modules replace faulty regular TSVs by fault-free spares. If the number of fault-free TSVs m is less than n and more than mLIMIT then the serialization / deserialization circuitry is enabled. Messages are serialized in the upstream interface by mapping only m out of n data bits on m fault-free TSVs until all the n bits of the message are transmitted. At the downstream interface, the received data bits are stored in a Deserialization Register in order to recreate the original message.
Even if an inter-die link is reparable (i.e. m 7 mLIMIT), the self-repair correctness may be compromised if errors occur during the diagnosis vector serial transmission from the upper to the lower layer. Faults on the DTRANS inter-die connection cause the repair logic to generate inconsistent repair signals. This connection is critical and protection against transient and permanent faults is ensured using triple modular redundancy
(TMR). The IBIRAS technique is independent on the link flow control protocol. The link control signals are routed on fault-free TSV in priority.
4.2.3.2 Self-repair circuitry
The self-repair strategy of IBIRAS consists in shifting each input signal bi by one or more positions, until reaching the first fault-free TSVs that is not yet occupied by another signal. The Reconfiguration Logic consists in a crossover switch and a combinational logic block that generates the switch control signals. In Figure IV-21, the MUX-implementation of the crossover switch is illustrated for a 4-bits link with four regular TSVs, W1-W4, and one spare W5. In this example, the link is functional if there are at least 2 fault-free TSVs (i.e. mLIMIT = 2). In the worst case, flits are sent in two transmission cycles.
W5 W4 W3 W2 W1
b1
b2
b3
b4
M1
M2
M3
M4 MUX3 MUX2 MUX1
MUX4
Figure IV-21 MUX implementation of the crossover switch in the reconfiguration logic
For n regular and r spare TSVs, the upstream Reconfiguration Logic crossover switch has n inputs and n+r outputs. If all regular TSVs are fault-free, each bit bi of the message is transmitted on TSV Wi. The crossover switch must be able to shift each input bi by n+r-mLIMIT positions for 14i4 mLIMIT-1, and by n+r-i-1 positions for mLIMIT4i4n-1, as the link is considered functional if there are at least mLIMIT fault-free wires. The MUXi control signals Mi are encoded as one-hot codes and they represent the number of positions each input bi must be shifted. Using the Mij notation (i.e. the jth signal of MUXi control signal Mi), for each input bi with 04i4mLIMIT-1, the Mi MUX control signals are Mi1-Min+r-mLIMIT+1; for each bj with mLIMIT4j4n, the Mj MUX control signals are Mj
1-Mj
n+r–j. The downstream Reconfiguration Logic is mirrored, as data signals received on the n+r TSVs are mapped on the downstream crossover switch n outputs.
The MUX control signals are computed using the diagnosis vector DV1-DVn+r. The equations of the control signals of MUX1 are simple, as the repair process starts from signal b1. These equations are:
1 1
1 1 1 2 2 1 1 1
1 DV,M DV DV,...,M DV DV ... DV
M = = ⋅ r+ = r+ ⋅ r ⋅ ⋅ (3)
The equations for MUXi control signals are more complex, as they have to take into account the fault-free TSVs already occupied by other positions. To reduce the cost of the logic generating them, iterative equations, which generate the control signals of position i+1 by using the control signals of lower order positions, are used. These equations are given below:
(
i j i i i i j)
j i j i j i j i j i j
i DV M M DV M DV DVi j M DV DV DV
M +1 = ++1⋅ + −1⋅ + + −2⋅ + −1⋅ + +...+ 1⋅ +1⋅ +2⋅...⋅ + (4)
The iterative equations (3,4) enable low-area hardware implementations of the repair function, but their recursive nature induces large delays. The DV values of their inputs are computed just once after the test and
diagnosis phase and remain constant until the next test phase. They stay unchanged during circuit normal operation and their delays do not impact the link timing.
4.2.3.3 Adaptive serialization circuitry
Link flow control signals are repaired in priority and they are connected to the less significant positions of the self-repair MUXes. As the number of control signals is small compared to the total number of TSVs, self- repair will ensure their repair. However, it is possible that the number of fault-free TSVs is insufficient for repairing the data signals. In this case, the serialization circuitry is activated to transfer data signals in several cycles. In Figure IV-22, the serialization and de-serialization circuitry is represented.
R O T A T E
SRN
SR2
SR1
…
COUNTER
TRUTH
TABLE PARALLEL CONTER rSHIFT
mSHIFT
R BUSY
K C ND
DV bN
b2
b1
RECONFIGURATION LOGIC
SE SE SE
(a) Configuration Logic
RECONFIGURATION LOGIC
S H I F T
DRN
DR2
DR1
…
COUNTER
TRUTH
TABLE PARALLEL CONTER rSHIFT
mSHIFT
R
K C ND
DV SE
SE
SE LSN
LS2
LS1
(b) Configuration Logic
Figure IV-22 n-bit Serialization (a) and Deserialization (b) modules without extra rotate cycle
Each of the serialization/deserialization modules comprises a configuration logic block that determines the internal control signals like the interface statues (BUSY), number of positions to rotate / shift the serialization / deserialization register content. These signals are determined using the interconnect test diagnosis vector DV.
The main phases of the adaptive serialization scheme are: load data bits in serialization register (SR), serial transmission from SR to deserialization register (DR), register contents rotate / shift and forward message from DR downstream.
In the first transmission cycle of the serialization/de-serialization process, the values coming from the mSHIFT right-most positions of the serialization register SR are transmitted and loaded into the mSHIFT left-most positions of the Deserialization Register DR. At the same time, SR rotates its contents by mSHIFT positions to the right to prepare them for the next transmission cycle. In the second transmission cycle, the mSHIFT right- most positions of SR are loaded into the mSHIFT left-most positions of DR, which also shifts its contents by mSHIFT positions to the right. At the same cycle SR rotates its contents by mSHIFT positions to the right. This is repeated at each transmission cycle except for the last rotation of SR (i.e. the one performed at cycle 3n/m4 - 1), which prepares the contents of SR for the last transmission cycle (cycle 3n/m4). During this cycle SR
rotates its contents to the right by R positions instead of mSHIFT positions, with R = mSHIFT if mSHIFT divides n and R = rSHIFT = n mod mSHIFT otherwise. Loading the incoming bits in the mSHIFT left-most positions of the deserialization register DR instead of the mSHIFT right-most positions (used in the previous section) is equivalent to rotating its content by mSHIFT positions to the right. Based on this observation, the extra rotation of mSHIFT positions can be eliminated, and the message is transmitted in 3n/m4 cycles, instead of 3n/m4 +1.
In order to load data from the mSHIFT right-most positions of SR into the mSHIFT left-most positions DR, the upstream Reconfiguration Logic is implemented to connect fault-free TSVs to its left-most outputs. As the reconfiguration is driven by DV, which points to the positions of the m fault-free TSVs, this solution will connect the m-fault free TSVs to the m left-most outputs of the upstream Reconfiguration Logic. To resolve this issue, a sequential circuit that modifies the content of the DV register by setting to ‘1’ all positions of DV after the first right-most positions containing mSHIFT ‘0’s. This way, the Reconfiguration Logic will consider all other positions as faulty and will connect the mSHIFT right-most fault-free TSVs to its mSHIFT left-most outputs.
DVn+r DV2 DV1
COUNTER mSHIFT Zero
DTRANS UPPER DIE
Figure IV-23 Circuit for diagnosis vector modification
In the circuit represented in Figure IV-23, the n+r flip-flops of the downstream DV Register are connected into a shift register configuration. The value mSHIFT is loaded in the counter. The counter decrements each time signal DV1 is ‘0’. The Signal Zero decodes the all 0s state of the counter. When Zero becomes ‘1’ it holds the counter, blocking it at its all ‘0’s state. After n+r shifts, the state of the diagnosis vector DV has been modified to DV’. The above operations are performed once after the test and diagnosis phase. Thus, computing DV’
they will not delay system operation, as it can be performed during DV serial transmission between dies.
In this section, data link solutions for TSV permanent faults have been presented. These solutions are based on well-known spare-based and serialization strategies. While TSV-SnR and CSL are aimed at TSV faults due to manufacturing, the proposed IBIRAS approach can be used with an efficient IBIST scheme to ensure high TSV reparability during system lifetime.