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Electrical Power and Energy Systems
journal homepage:www.elsevier.com/locate/ijepesReal-time boundary wavelet transform-based DC fault protection system for
MTDC grids
Lorenzo Sabug Jr.
a,⁎, Aysar Musa
a, Flavio Costa
b, Antonello Monti
aaInstitute for Automation of Complex Power Systems, E.ON Energy Research Center, RWTH Aachen University, Mathieustraße 10, 52074 Aachen, Germany bUniversity of Rio Grande do Norte– School of Science and Technology, Campus Universitario Lagoa Nova, Natal 59.078-970, Brazil
A R T I C L E I N F O Keywords: DC fault protection MTDC grid RT-BWT method A B S T R A C T
In this paper, the real-time boundary wavelet transform (RT-BWT) method is proposed for dc fault protection in multi-terminal high voltage dc (MTDC) grids. The proposed method is developed and tested in a real-time simulation platform. A wide range of test scenarios have been adopted considering ac and dc fault conditions, including variations in fault resistance, fault event distance, dc reactor inductance, external fault events, and changes in topology. The results and statistical analysis show the effectiveness and performance of the RT-BWT method in providing fast, sensitive, selective, and robust dc fault protection, even without the need for com-munications.
1. Introduction
The growing importance of offshore wind farms, renewable energy integration, and international bulk power exchange has motivated re-search interest in high-voltage dc (HVDC) systems. In particular, HVDC grids based on voltage-source converters (VSC-HVDC) have attracted attention due to the independent control of active and reactive power, and no need to reverse the voltage polarity to change power direction [1]. These advantages lead to the deployment of several VSC-based multi-terminal HVDC (VSC-MTDC) grids[2,3].
However, dc fault handling in VSC-MTDC grids (referred in this paper simply as MTDC grids) is a major challenge due to its fast dy-namics, particularly the rapid rise of the fault current, exceeding the short-circuit limits of the converters’ anti-parallel diodes. DC faults propagate from the fault location to other healthy parts in the MTDC grid, and even further to the tied ac grids[3], which may cause cas-cading failure and blackouts. Hence, fast and selective protection methods are required to identify and discriminate the faulted line, isolate the dc fault, and maintain power flow continuity in the non-faulted parts in the MTDC system [3]. Early proposed schemes for MTDC protection[4]disconnect all tied ac systems (by opening the ac breakers) before opening the dc breakers around the faulted line. This scheme, in principle, stops the entire MTDC grid operation upon fault detection, which is unacceptable for large MTDC grids[5].
Several selective methods have been proposed for MTDC protection recently, mainly based on the travelling wave and rate-of-change
measurements. The traveling wave principles have been used for MTDC fault detection and location[6]. However, the method’s accuracy is not proven with regards to differentiating dc faults and non-dc fault events, e.g. ac faults, and converter blocking/deblocking. A travelling wave-based technique is also proposed in[7], achieving detection via surge arrival time difference between 2 travelling waves. However, the pre-sence of blind zones in the proposed protection means that remote signaling– and communications – is still needed especially for faults occuring in the end of a line. This blind zone can be minimized by increasing the frequency, however, the method cannot be used to detect the more critical pole-to-pole faults.
Recognizing dc line reactors as boundary for high-frequency com-ponents of the fault transient, voltages across dc reactors were used in [8–12].[8]proposed a method with a criterion based on the rate of change of voltage (ROCOV) on dc reactors. This voltage is dependent on the dc reactor inductance, which compromises the method’s robustness with dc reactor sizes, which can differ among substations depending on the respective operators’ requirements. [9] proposes using another metric for fault detection, the ratio of transient voltage (ROTV) of dc reactors. This technique however requires long-distance communica-tion between computacommunica-tional units from opposite ends of the line in order to work accurately. A wavelet-based technique is proposed in [13], which enables PP and PG fault detection, together with faulted pole identification. The use of an integration over a fixed time window of the transient energy, introduces minimum time delay before actually sending the tripping signal to the relevant breakers, which is
https://doi.org/10.1016/j.ijepes.2019.105475
Received 31 March 2019; Received in revised form 15 July 2019; Accepted 5 August 2019 ⁎Corresponding author.
E-mail address:[email protected](L. Sabug).
Available online 19 August 2019
0142-0615/ © 2019 Elsevier Ltd. All rights reserved.
undesirable especially in metallic PP faults. This delay, added with the breaker operation delay, can contribute to higher power losses due to late tripping. Furthermore, measurement of only the transmission line-side voltages make it highly difficult to recognize converter-line-side dc faults. In[10], a ROCOV-based protection scheme is proposed using the dc reactors. [11]proposes a simple detection scheme using voltages across the dc reactors.[12]uses dc line-side voltage of the dc reactor to detect fault events, however, it waits for a peak time before classifying a fault, which introduces delays which is undesirable especially with metallic faults. Furthermore, it also ignored normal operation events like operation change, and also external ac faults.[10–12,14,15]did not consider corner cases of internal converter faults, a worst-case scenario that might induce additional misdetections and mistrips.
In[16], a method is proposed for the protection of MTDC grids by using the voltage and current wavelet coefficients through the sta-tionary wavelet transform (SWT). The SWT provides a time-invariant transformation property, which overcomes the limitation of the discrete wavelet transform (DWT) for fast detection of transients induced by faults in real-time applications[17]. However, both the DWT and SWT present limitations in the real-time detection of fault-induced tran-sients, such as inability to detect overdamped transients such as in high-impedance faults, and considerable time delay for long wavelets. Nevertheless, the real-time boundary SWT, termed in this paper as RT-BWT, is scarcely affected by such problems[18–20].
In this paper, a simple dc fault detection and protection method is proposed for MTDC systems based on the RT-BWT. The paper puts forward the following contributions:
1. Fast, accurate and selective RT-BWT algorithm for fault detection in MTDC, effective even with damped transients, e.g. due to high-re-sistance faults.
2. The proposed method uses only local measurements; there is no need for communication and synchronization among far-away nodes. Effectiveness of the method is demonstrated in this paper even on low sampling frequencies of few kHz, making it attractive for deployment on mid-range or low-end hardware.
3. The deployment of the proposed method, and its verification in real-time simulator, demonstrates its feasibility in a real protective relay. The comparison testbench in terms of the effects of the mother wavelet is the SWT. In addition, this paper presents sensitivity analysis to fault resistance, fault distance, dc reactor inductance, sampling fre-quency, external faults, and normal operation condition changes. The results are discussed regarding the effects of these factors on the dc fault protection performance. A comparison with the recently-proposed dc fault detection from [8] is presented, highlighting the performance difference of both techniques especially in corner cases. Representative fault scenarios are presented in real-time simulation, investigating the feasibility of implementing the method in a real protective relay and integrating with the dc breaker actions. Lastly, statistical results show the selectivity of the method, and detection delays, even with changes in the MTDC grid topology.
This article is organized as follows. Section2describes the test grid configuration and its specifications. Section3introduces the RT-BWT, followed by a description of the proposed fault detection and protection strategy in Section 4. Section 5 describes the real-time setup, while Section6 and 7 present fault transient studies representative results with the RT-BWT-based technique. Finally, Section 8summarizes the findings and results.
2. System configuration
The MTDC test grid configuration considered in this study is shown inFig. 1, representing offshore wind farms supplying power to onshore ac grids. The MTDC grid is laid out in a symmetric monopolar topology. Each converter terminal is based on the modular multilevel converter
(MMC), which is a promising topology for future MTDC systems due to features such as modularity, scalability, and low switching losses[21]. Wind farms 1 and 2 connect to substations MMC2 and MMC4, while ac grids 1 and 2 receive the transmitted wind farms power through MMC1 and MMC3.
2.1. Converter topology and control
Each terminal is a 401-level MMC converter with 400 half-bridge submodules per arm. On the dc side, the positive and negative dc poles of each terminal MMCx are connected to the corresponding dc bus Bx. On the ac side, all MMCs use Y/Δ coupling transformers to interface to respective ac systems. A detailed equivalent Thevenin-based model [22,23]is used for the MMCs in real-time simulation. More information about the MMCs are inTable 1based on[24].
Control of all MMC terminals are composed of high-level and low-level control as in[25]. The onshore grid-side inverters MMC1 and MMC3 use Vdc-P droop control on d-axis (Vdc ref, =640 kV,
= = −
βdroop 0.01,Pref1 400MW,Pref3= −400MW where positive P means active powerflowing into the MTDC grid) while offshore wind farm-side rectifiers MMC2 and MMC4 use active power P control on the d-axis (Pref2= +350MW,Pref4= +600MW). All ac grid-connected MMCs implement reactive power Q control on the q-axis, while wind farm MMCs useVac control. As the paper focuses on the detection/dis-crimination of dc faults and opening of the correct dc breakers with a time horizon of several ms, the post-fault islanded operation of wind farms are not considered. For VSC control schemes in wind farm is-landed operation, readers are recommended to refer to[26].
2.2. AC systems
All ac systems, including the onshore ac grids and offshore wind farms, are represented by constant 230 kV 50 Hz sources placed behind an impedance, such that the resulting short circuit ratio (SCR) is 10. This assumption represents a worst-case scenario with a strong ac side, which can feed the fault with large current.
2.3. Transmission lines
Four 450 km undersea links connect the terminals in a rectangular topology, each composed of two cross-linked polyethylene (XLPE) submarine cables rated at 320 kV. The cable physical specifications are based on[27], and summarized inTable 2. To achieve accurate fault transients, the frequency-dependent model (curvefitted in a range from 0.001 Hz to 1 MHz) is used for the cables in the simulator.
2.4. Protection devices
Hybrid dc breakers are located on both ends of each transmission line, and between each converter terminal MMCx and its nearest dc bus Bx. The detailed hybrid dc breaker operation is based on[28]. How-ever, the simulated model used is a simplified model from[25]. This model is composed of an ultra-fast disconnector (UFD), parasitic series inductance Ls, line commutation switch (LCS), main breaker (with parallel zinc-oxide surge arrester rated at 1.5 times dc pole voltage), and residual dc breaker, with a schematic shown inFig. 2. At normal operation, the bulk currentflows in path a [Fig. 2] through the LCS and UFD, i.e. these switches are closed, while the main breaker is open. At dc fault detection, the LCS opens, the UFD starts to open, and the main breaker closes, redirecting the fault current to path b. After a 2 ms operation delay, the UFDfinishes opening, and the main breaker opens as well, leading the current to the arrester (path c), which decreases the fault current towards zero. This allows the residual dc breaker to open at low current, leading to physical disconnection. Important speci fica-tions assumed in the hybrid dc breaker are summarized inTable 3. In case of PP dc faults, both the positive- and negative-pole breakers for
identified points are opened. Given that PG dc faults cause high pole overvoltages up to twice the nominal voltage[29], breakers at both poles are likewise opened.
The MMC converters are equipped with valve overcurrent protec-tion with 2 kA threshold. DC reactors of 100 mH are on both ends of each line to limit fault current rise, and consequently, the current peak value[5]. Surge arresters, rated at 1.5 times the dc pole voltage rating
[30], are placed on both poles of the converter terminals. In the si-mulator, a simplified model with a piecewise linear v-i behavior is used as in[31].
2.5. Nomenclature
The dc link voltage as seen on MMCx isVBxbecause its terminals are connected to Bx. Bus Bx is connected to bus By through transmission line Lxy. Furthermore, the dc reactor around Lxy which connects from Bx (By) is Dxy (Dyx). The current through Lxy from Bx to By (By to Bx) is IDxy(IDyx). Lastly, BRKxy (BRKx) is the breaker associated with Dxy (MMCx). Locations for considered fault events in this paper are marked in Fig. 1. Faults are defined as internal when they occur inside the protection area of a certain BRKxy, i.e. faults at Lxy; otherwise, they are regarded as external.
3. The real-time boundary wavelet transform
Consider x as a discrete time-domain signal whose samples are obtained in real-time and k as the current sampling associated with the timek f/s, where fsis the sampling rate. The boundary wavelet coe ffi-cients w l k( , ) are computed through inner products between L coe ffi-cients of the waveletfilter hψ and L samples of the signal x inside a circular sliding window with length N (x∘), defined as follows[20]:
∑
⎛ ⎝ ⎜ ⎞ ⎠ ⎟ = ⎛ ⎝ ⎜ − + + + ⎞ ⎠ ⎟ = − ∘ w l k, 1 h n x k L n l 2 n ( ) 1 , L ψ 0 1 (1) where0⩽ <l L L; ⩽N k; >N−1; (x k∘ +m)=x k( +m) if −N<m⩽0 andx k∘( +m)=x k( −N+m) if0<m⩽L; and L is the length of the waveletfilter hψ. w(0, )k =w k( ) are coefficients with no border dis-tortions (similar to the RT-SWT coefficients), whereas w l( ≠ 0, )kpresent border distortions.
In real-time, the wavelet coefficient energy of the RT-BWT is given by[18,19]:
∑
∑
= + = − = − + k w n k w m ( ) [ ( , )] [ ( )] , w n L k m k N L k k 1 1 2 ( ) 2 ( ) wa wb (2)Fig. 1. MTDC test grid configuration.
Table 1
MMC converter parameters.
Property Value
Base electrical quantities
Vdc base, 640 kV
Vac base, 370 kVLL
Sbase 1000 MVA
MMC specifications
Rated dc link voltage ±320 kV
Rated ac voltage 370 kV
Submodule capacitance Csm 10 mF
On (off) submodule resistance 5 mΩ (100 MΩ)
Arm inductance Larm 50 mH
Coupling transformer leakage reactance Xt 0.15 p.u.
Table 2
MTDC cable physical parameters.
Layer Thickness (mm)
Conductor (stranded copper) 24.9
Conductor screen (semi-conductive polymer) 1
Insulation (XLPE) 1
Insulator screen (semi-conductive polymer) 1
Sheath (lead) 3
Inner jacket (polyethylene) 5
Armour (steel) 5
Outer cover (polypropylene) 4
Fig. 2. Simplified hybrid dc breaker model used in simulator.
Table 3
DC circuit breaker specifications summary.
Description Value
Ls 100 μH
Residual dc breaker closed resistance 5 mΩ
UFD closed resistance 5 mΩ
LCS closed resistance 30 mΩ
sincek⩾N−1; the superscript indices a and b indicate the energy components with and without border distortions, respectively.
The RT-BWT is superior in comparison to the conventional SWT in terms of suitability for real-time samples. Although SWT is widely used in the literature even with real-time samples, some issues arise when using real-time data. As an example shown inFig. 3, consider a mea-surement which is acquired in real-time. After a data stream of a quiescent value, thefirst transient/disturbance data samplex k( )arrives at timek f/s. In this case, the data set only has this newest transient samplex k( )and any previous samples, i.e. there are no future samples. In SWT, thex k( )is only aligned with the last mother wavelet coefficient (a small value), which means that at the discrete time k, the SWT coefficient is still a small value, and several samples are needed for the
x k( )to align with the center part of the mother wavelet. This results in a time delay for the SWT response, especially with longer mother wa-velets. To solve this problem, the RT-BWT takes thefirst samples in the sampling window and effectively creates a circular buffer [Fig. 3(b)]. In effect, for a first transient sample coming in at discrete time k, there are already samples to the right of it (composed offirst data in the sampling window), and the SWT (with border effects) can proceed with the transient sample aligning already with the middle of the mother wa-velet.
The performance of the RT-BWT is affected by the chosen mother wavelet. As the Haar wavelet has weak high-passfilter properties, low-frequency oscillations (as when ac fault transients penetrate to the dc side) will have effects on the generated boundary wavelet coefficient energies. On the other hand, the Daubechies wavelets have better high-pass properties, and are recommended for usage in the proposed fault protection technique. Longer Daubechies wavelets converge to an ideal high-pass filter, offering more effective fault transient detection, but they impose much higher computational burden. In this paper, db4 wavelet is used because it offers good low-frequency disturbance re-jection, and has low computational burden. In this paper, dbL means a Daubechies mother wavelet with waveletfilters and L coefficients.
The sampling frequency can be set based on the desired detection speed and the limitations of the hardware to which it will be im-plemented. However, as the RT-BWT wavelet coefficient energy mainly highlights the high-frequency transients, there are some constraints that need to be fulfilled. For example, depending on the relative frequency response of the mother wavelet, fs should be selected such that the resulting frequency response of the mother wavelet effectively attenu-ates low frequencies, including the ac frequency fundamental (50 Hz or 60 Hz, according to area). In this paper, fsis set to 10 kHz.
For applications in ac fault detection[19],N=f fs/owhich increases with higher fs in order to fit one cycle into the sampling window. However, there is no fundamental period for dc signals, which trans-lates toflexibility for choosing N. A longer window means an increased border effect contribution on the RT-BWT wavelet coefficient energy at the onset of the fault transient, however, this requires larger memory
and larger resource overhead due to memory access. On the other hand, the minimum window length is given as2L−1, to accommodate the calculation of the border effect energies. The RT-BWT sliding window size is chosen asN=40 in this paper to minimize storage use.
4. Proposed DC fault protection strategy
The proposed method measures the voltages across the dc reactors Dxy to detect dc fault-related transients via RT-BWT. Voltage sensors are installed on the positive and negative poles of an MTDC node j as shown inFig. 4, resulting in a measurementvx=vx+−vx−wherevx+ andvx− are the positive and negative pole voltages with respect to ground, respectively. A voltage sensor pair is installed on the bus, and a pair is placed on the line side of each dc reactor. This results inM+1 sensor pairs around Bx, where M is the number of lines connected to Bx. In the discussions that follow, voltage measurementvxis the potential difference between the positive pole and the negative pole.
The voltage across the dc reactor Dxy isvDxy=vBx−vDxy l, where vBx is the voltage at dc bus Bx (where Dxy is connected), and vDxy l, is the voltage at the transmission line side of Dxy. For the proposed technique, the RT-BWT wavelet coefficient energy of vDxy, referred asDxyw , is cal-culated. TheDxyw is irrespective of power transmission direction, hence the sensor layout, as well as the definitions of vDxyandDxyw are the same across all buses Bx.
4.1. Fault detection criteria and algorithm
The dc fault detection is composed of two criteria: detection of the RT-BWT wavelet coefficient energy levels, and confirmation by mea-suring the speed of its rise. The first criterion is fulfilled when at a sampling instant k, the RT-BWT wavelet coefficient energy Dxyw ( )k
ex-ceeds a set threshold EDw. The second criterion is based on the rise speed of wDxy referred as the threshold rationth, the ratio of wDxy at surrent sampling k to a previous value atk−Z, shown as follows:
Fig. 3. Difference of (a) SWT and (b) BWT in the context of real-time samples.
Fig. 4. Sensor layout and voltages measured for the proposed RT-BWT-based dc fault protection scheme.
= − n k k Z ( ) ( ) th Dxy w Dxy w (3) where Z is a small number and is set asZ=2in this study. A threshold
Nthshould be exceeded bynthto serve as a confirmation of a fault event. The calculations required are carried out on a computational unit on each dc bus Bx, taking only local measurements for connected dc re-actors Dxy. Hence, the proposed method does not need communications among neighboring buses. Additionally, there is no requirement for synchronization among the computational units with regards to the measurement timing. Note that thefirst-level decomposition is required for the proposed technique, as it is found that thefirst-level RT-BWT wavelet coefficient energy is already sufficient for the proposed tech-nique to differentiate the relevant faults from non-relevant events.
A comparison among representative techniques for dc fault detec-tion is summarized in Table 4, laying out the advantages and dis-advantages of the proposed RT-BWT method. While other methods suffer from issues in sensitivity, selectivity and/or detection delays, the proposed RT-BWT-based technique presents advantages especially in case of accurate differentiaion of the relevant faults and irrelevant events. This is in combination with a minimal detection delay, which is due to the introduction of the border effects as discussed in Section3. Furthermore, the feasibility of the proposed method even with rea-sonably low sampling frequencies and no communications drives down the costs, making it attractive for real-life implementation. These ad-vantages and properties are demonstrated in this paper through simu-lations and statistical tests, as will be presented in Sections6 and 7.
Theflowchart for the proposed fault protection method is shown in Fig. 5. At every time instantk f/s at sampling frequency fs, the fault protection decision unit at Bx collects measurements vDxy for all con-nected Dxy. The calculations for each EDxyw ( )k evaluates which dc
breaker/s BRKxy might be candidate/s for tripping. If a single dc re-actor Dxy measures a possible fault, i.e. if both criteria are fulfilled for Dxyw ( )k , it immediately sends the trip signal to the corresponding
breaker BRKxy. However, if multiple connected dc breakers BRKxy1, BRKxy2,…BRKxycare evaluated as candidates for tripping at the same instant k, it selects the BRKxytrpfor opening according to the highest Dxyw ( )k . The highest ( )k
Dxy
w means that BRKxy
trpmeasured the strongest transients, which implies that the fault must have occurred on its pro-tection area. This way, the other candidate breakers do not trip, i.e. their operations are muted. However, if Dxyw ( )k for all candidate
breakers are within 0.1% of each other, it is generally regarded as a fault in the bus. Given the MTDC test grid configuration in Section2 where the MMC terminals are directly connected to the bus, this is interpreted as an internal converter fault. BRKx is opened, dis-connecting MMCx from the MTDC grid.
The accuracy of the proposed fault detection method is unaffected by the breaker model and control dynamics. From the inception of the fault, the voltage and current transient response of the MTDC grid on thefirst few ms is mainly only affected by the grid topology and dc line characteristics. Since the breakers in this time horizon can be modelled by a short circuit (since it is not yet tripped), the fault detection will not be influenced by the breaker dynamics. After detection and upon trip-ping of the relevant breakers, however, the breaker dynamics might induce more transients that can propagate to other sides of the MTDC grid. This concern is addressed in Section7. Additionally, the time horizon for dc fault transients is too short for the control dynamics to respond significantly. Hence, the MMC control will not have consider-able effect on the effectiveness of the proposed protection scheme. 4.2. Fault detection thresholds setting
To set the thresholds EDwandNthfor use in fault recognition, several simulations are performed on the target grid, focusing on the critical cases:
Table 4
Comparison of representative fault detection schemes for MTDC grids.
Description of scheme Advantages Disadvantages
Conventional overcurrent[32] Simple concept and implementation. Almost no computation required. Prone to false positives. Further criteria required to correctly differentiate a fault.
Travelling wave[6] High fault source location accuracy. High sampling frequency and time synchronization required among
terminals, translating to higher investment cost. Differentiation of fault events from false positives not demonstrated.
DC reactor voltage rate of change[8]
Simple implementation. Agnostic of powerflow direction. EMI robustness improvement over conventional rate-of-change based methods. No communication required.
Accuracy not verified for faults at converter terminal, other corner cases.
Surge arrival time difference[7] Works on systems without boundary components on dc lines. Minimal computational burden.
Presence of”blind zones” does not cover the whole protection area. Needs communications especially for faults on line ends. Discrete wavelet
transform-based[13]
Excellent differentiation between relevant and irrelevant events. No communication required.
Requires a minimum time delay before detection. Detection speed dependent on mother wavelet.
Real-time boundary wavelet transform (proposed)
Sensitive and fast reaction time, even for damped transients. No time delay usually associated with using longer wavelets. No communication required, and works with low sampling frequency, leading to low investment costs. Excellent differentiation between relevant and irrelevant events.
Higher computational burden if using longer mother wavelets.
•
minimum individualDwandnthat dc faults, e.g. values that should still detect the fault.•
maximum individualDwandnthfor external events, e.g. values that must not be misrecognized as a fault.The thresholds are then set between these minimum fault and maximum non-fault values. Uncertainties and changes in MTDC grid parameters might introduce overlaps in the maximum non-faultwDand minimum faultDw. However, usingnthas confirmation is found effec-tive in differentiating internal and external faults due to the wide gap between the maximum non-faultnthand the minimum faultnth, even with changes in MTDC parameters and topology.
A simple procedure for setting the thresholds EDwandNthis described below. As an example of simulations that are selected to set the thresholds, BRK12 is considered, as shown inFig. 6.
•
Choice of corner cases. BRK12’s relevant protection zone is the line L12, i.e. any fault that occur within this line is a relevant fault, and all events in other locations are irrelevant. The weakest relevant fault (resulting in minimumDwandnth) that BRK12 should detect is a high-resistance PG fault (250 Ω for example) at the farthest end of L12 (adjacent to D21). This fault scenario can be denoted as FminBRK12. On the other hand, the most critical cases that may cause mis-detection at BRK12 are a PP metallic fault at MMC2. This case, denoted as FmaxnBRK12, might overlap with FminBRK12due to their expected stronger transients and electrical proximity to the location of FminBRK12.•
Extraction ofD maxw, andnth max, for corner cases. Obtaining these values might require the first 2–3 ms of the transient response and its correspondingDw12. For scenario FminBRK12, denote the maximum RT-BWT coefficient energy as Dw12 ,+max. The corresponding maximum for FmaxnBRK12can be denoted asDw12 ,−max. On the other hand, nth max, is extracted by applying(3)to samples in the time window, with the maximum values resulting to the notationsnth max, +andnth max, −.
•
Setting the differentiation thresholds. The thresholds EDwandNthshallbe set to cover FminBRK12, but not FmaxnBRK12. As the conditions for tripping BRK12 areD12⩾ EDwandnth⩾Nth(note the and operator), EDwand
Nthare set less thanDw12 ,+maxandnth max, +, respectively. The irrele-vant corner case value wD12 ,−max might exceed the setting EDw. However, a clear gap is present betweennth max, +andnth max, −, hence theNthcan be comfortably set between these values. An example for setting the thresholds is shown inFig. 7.
It is well known that the fault transient characteristics, as well as their resulting RT-BWT energies are dependent on several intertwining factors, which may affect and pose challenges to the setting of the thresholds. Section6presents an in-depth study that shows major fac-tors, and their effects on the fault detection performance.
5. Implementation in HIL test bench setup
The dc fault detection scheme is implemented in an FPGA board for
HIL verification, to demonstrate the viability of applying the proposed RT-BWT algorithm in real hardware.
5.1. HIL test bench overview
The HIL test bench is composed of the FPGA board and two racks of the Real-Time Digital Simulator (RTDS, referred henceforth as the real-time simulator or simply simulator), connected via optical cable. A diagram of the HIL setup is shown inFig. 8.
The simulator executes the model of the MTDC grid, and calculates the power network and transient solutions in real-time. For every si-mulation step, the simulator sends the dc reactor voltages (VDxy) to the HIL FPGA board.
The HIL FPGA board, embedding an XC5VFX70T FPGA, functions as a RT-BWT-based dc fault detector in dc bus B1 [Fig. 1]. The RT-BWT algorithm is implemented in Verilog, and deployed in this FPGA. For each value sent by the simulator, the HIL board computes the required wDvalues, and sends them back serially through the optical link. The real-time simulator acquires the coefficient energies, plots them, and uses them for the breaker trip activation logic. The FPGA im-plementation is chosen as an example in the paper due to the avail-ability of an convenient interfacing scheme with the real-time simula-tion using the GTFPGA intellectual property (IP) core. However, given the light computational burden and low sampling frequency used, the algorithm can be directly implemented without any problems on a CPU or DSP controller, both of which have more than the necessary com-puting power for the task.
5.2. RT-BWT implementation example in FPGA
The number offloating-point operations (FLOPS) per sampling in order to computeDwis given by[33]
= + −
flop( Dw) L(2L 1) 1 (4)
The worst-case computational delay for the algorithm occurs when only one memory or arithmetic operation is performed at a time. The delay in(4)is quadratic with respect to L, hence a compact mother Fig. 6. Choice of corner cases for threshold setting.
wavelet is preferred to minimize it. Another way to minimize the delay is to do parallel computation to make the inner products faster, which is implemented in the FPGA.
Memory read and write delays are linear with respect to L[33]. Hence, for a larger L, the effective computational delay is dominated by (4). However, larger N means higher required memory allocation, which might be an issue when using many RT-BWT calculators in a single device, e.g. for calculating RT-BWT coefficient energies for many dc reactor voltages connected to a bus.
5.3. Real-time simulator setup
The developed FPGA device is used as the dc fault detector device for the MMC terminal MMC1 as shown inFig. 1. For the other dc buses B2-B4, the proposed fault detection scheme is implemented inside the power simulator using custom components, programmed in C.
The simulator runs with a simulation frequency of 20 kHz (50 μs timestep). In the simulation, the MMCs are contained inside a sub-timestep module which perform switching calculations every 2.5 μs to achieve accurate MMC transients [34]. The FPGA runs the RT-BWT calculations at 10 kHz, performing a data exchange with the simulator per 2 timesteps. This can be understood as the regularly-timed transfer of sensor measurements (represented by the simulator variables) to the computational unit, and the sending of control signals to the appro-priate breaker actuators if fault is detected. The full-loop data trans-action between the simulator and the FPGA shouldfinish within one timestep.
Current technology allows for dc voltage measurements with fre-quency response of up to the MHz-range[35]. Given the relatively low sampling frequency that the proposed RT-BWT technique demands, the effects of dc voltage measurement bandwidth can be reasonably ne-glected. This is an advantage compared to travelling-wave techniques with sampling frequency of up to few MHz, and whose effectiveness can be affected by the measurement bandwidth.
6. DC fault studies with RT-BWT
Several scenarios are discussed in this paper to study the perfor-mance of the proposed RT-BWT-based fault protection scheme in terms of speed, accuracy, and selectivity. The verification of the proposed technique is presented in two parts: effects of fault parameters on the detection (without dc breaker action, in this section), and effects of dc breaker action (in Section 7). It is well known that the system-level performance of a protection scheme also depends on the breaker
technology used, with operating time horizons ranging from 2 to 5 ms [36]. However, slower-tripping dc breaker types might allow transient signals to propagate throughout the MTDC grid and cause mistripping even on faraway dc breakers. Hence, this section can be treated as a study when the breaker operation delay is larger than the estimated 2 ms for a hybrid dc breaker, that the transient signal has already propagated to the whole MTDC grid.
It is assumed that each MTDC bus has its own fault detection unit, and computes the necessary dc fault detection-related values from local measurements. Each computation unit performs fault recognition on its own, and communications are assumed to be absent. All dc breakers are disabled in order to study and present the full transient response after the fault event. This means that the fault transients proceeded without intervention from the proposed fault protection scheme. However, Section7shows representative fault scenarios to investigate the effects of dc breaker tripping on the effectiveness of the proposed method as aforementioned, i.e. all transients are now affected by the fault pro-tection after the relevant breakers are tripped. Following the steps de-scribed in Section4.2, the threshold EDwis set as101.25=17.783, andNth is101.75=56.234.
In Section6.1, a comparison between the conventional RT-SWT and the proposed RT-BWT is shown, highlighting the advantages of the latter to the former for dc fault detection. In addition, the next Sections 6.2–6.4present and contrast the performance of RT-BWT and the dc reactor voltage change rate (RVCR) method proposed in[8], where effects of varying the fault resistance, fault distance, dc reactor in-ductance, and external faults are studied. As a summary, the RVCR method is a distributed fault detection method which measures the time
tctaken by the dc reactor voltage to cross two thresholds Vth,1and Vth,2, whereVth,2>Vth,1. A fault is detected when tcis less than a set threshold
Tc th, , meaning that the dc reactor voltage has high enoughdVdt to indicate a relevant fault event. Iftc>Tc th, , the transient is not recognized as a dc fault, and no breakers are tripped. In this study, the thresholds are set as
=
Vth,1 5kV,Vth,2=10kV, andTc th, =150μs. If two sibling dc reactors (connected to the same terminal, e.g. D12 and D13) detect the same
<
tc Tc th, , the one with the higher dc reactor voltage swing amplitude (VDm) is tripped. More information regarding this technique can be seen in [8]. The RCVR algorithm is done by post-processing the acquired waveforms in MATLAB, and measuring the tc for fault identification, taking into account every timestep. This means that the RCVR sampling rate in this study is 20 kHz, which is twice that of RT-BWT.
6.1. The RT-SWT versus RT-BWT for DC fault detection
The main concerns in wavelet-based real-time fault detection are time delay and accuracy, which are usually associated with the mother wavelet.Fig. 9shows a dc reactor voltage VD24, recorded at a 200 Ω PG fault at L24, 225 km from MMC2 (location F inFig. 1). Furthermore, the wavelet coefficient energies wDusing mother wavelets db4, db8, and db16 are in thefigure, where dbL means a Daubechies mother wavelet with L coefficients. Some wavelet coefficients w are also shown. Both the conventional RT-SWT and RT-BWT algorithms are considered.
For the sake of illustration simplicity, the wavelet coefficient en-ergies in thefigures are normalized to present values around one in the steady-state period, and plotted in logarithm scale to highlight the fault detection and time-delays. If necessary, linear scale is shown as zoom to highlight differences between energy magnitudes. The wavelet coeffi-cients are normalized to present values between−1 and 1 during the steady-state period.
The RT-SWT wavelet coefficient w(0, ) of db4 presented a con-k
siderable increase at the fault inception time without time-delay [Fig. 9(b)], whereas w(0, ) of db16 ink Fig. 9(c) presented time-delay for the fault detection and the lowest peaks associated to the fault-in-duced transients. Indeed, the RT-SWT wavelet coefficients present dif-ferent time delay and accuracy in the fault detection with the choice of the mother wavelet. It is well-known that the db4 is one of the best choice for fault detection. However, there are critical faults with overdamped transients where even the db4 RT-SWT wavelet coe ffi-cients w(0, ) can failk [20].
The RT-BWT presents four wavelet coefficients by using the db4 mother wavelet, and all of them can detect the fault. For instance,
w(1, ) presented higher increase than wk (0, ) (component of both RT-k
SWT and RT-BWT) at the fault inception time, and without time-delay
[Fig. 9(b)]. In the same fashion, w(2, ) presented also relevant valuesk
and no time-delay in contrast to w(0, ) of db16 ink Fig. 9(c). Indeed, there is at least one of the RT-BWT wavelet coefficients which presents no time delay. In addition, since the RT-BWT wavelet coefficients are affected by both fault-induced transients and border distortions, they are affective for detecting critical faults with overdamped transients. A complete description about these properties in ac fault detection can be found in[20].
Regarding the wavelet coefficient energies, the resulting Dw24 for RT-BWT [Fig. 9(d)] has performed consistently across the different mother wavelets becauseDwb
24considers w(0, ) and all the boundaryk wavelet coefficients (no time delay). In contrast, the response of con-ventional wavelet coefficient energiesDwb
24was slower for longer wa-velets [Fig. 9(d)] because only w(0, ) is considered. Regarding thek
accuracy, the RT-BWT energyDw24 considers both the transients and border effects, whereas the RT-SWT energy Dwb
24 considers only the transients (Dw24≫Dwb24). For instance, the RT-BWT was the most sen-sitive for the fault detection inFigs. 9(d) and (e). According to[19], even critical faults with overdamping transients can be detected through the RT-BWT.
The observations for the wavelet coefficient energies agree with the ac fault signal analysis from[19], and confirm the advantage of the proposed RT-BWT in terms of response to transients, which are of es-sential importance for dc fault detection. Since the RT-BWT is scarcely affected by the mother wavelet for dc fault detection, the db4 was se-lected due to its low computational burden, and due to its better fre-quency response than the comparably compact Haar wavelet[20].
6.2. Effect of fault resistance 6.2.1. DC transmission line fault
A PG fault in line L13 (150 km from MMC1, location C) is studied with Rf varying from 0 Ω to 100 Ω. Rf is expected to have direct effect on the voltage and current responses at the affected line, withRf =0Ω resulting in the fastest transients, and becoming more damped with increasing Rf.
Fig. 10(a) shows the bus voltage at MMC1 and MMC3 (the terminals surrounding the affected line L13) for the first 50 ms after the fault event. Notable, especially at Rf=0Ω, is the operation blocking of MMC1 and MMC3, making both bus voltagesVB1 andVB3 to plunge down several ms after the fault event. This is due to valve currents exceeding the 2 kA threshold, as inFig. 10(b). This operation block also caused all MMC switches to open, stopping the average MMC capacitor voltages VC1andVC3(average of all cells, in both arms and all phases) from discharging [Fig. 10(c)].
However, the responses are more and more damped at higher Rf, most evident withRf =100Ωand above.Fig. 10(e) shows the dc vol-tages across the reactors D13 and D31 at the same time interval, de-noted asVD13 andVD31, respectively. BothVD13 andVD31 resulted in correspondingly attenuated response with increasing Rf [Fig. 10(e) inset]. However, the voltage transients for the both D13 and D31 are highlighted in their respective wavelet coefficient energies Dw13 and wD31 even for high-resistance faults, which abruptly rose around 5–8 orders of magnitude upon fault wave arrival to the respective nodes.
BothDw13andDw31exceeded the set EDw, which means that BRK13 and BRK31 will trip. However, the faint gray lines show that someDw for external breakers also intersected with the threshold EDw at the considered time interval. Hence,nth is used for confirmation of the fault. These observations are summarized inTable 5showing the RT-BWT metrics for thefirst 7 ms after the fault. In the data, the fault is recognized only in the correct breakers BRK13 and BRK31. The wavelet coefficient energies at other terminals MMC2 and MMC4 either did not exceed EDw, or did not have the required rise speed (lownth).
For comparison, the results of the RVCR is shown in the lower half ofTable 5, showing tc(in ms) and Vdm(in kV) values for each dc reactor, showing D13 and D34 having fulfilled the criteria for fault detection, Fig. 9. Effect of changing the mother wavelet, (a) VD24; (b) w (db4); (c) w
with also D12 and D34 at low Rf. Values of tcwere same for D12 and D13 atRf =0ΩandRf =10Ω, hence their VDmare compared, which led to selection of D13 (D12 is muted). On the other hand, tc for D31 is clearly less than that of D34, hence it was automatically selected. As a result, the correct relevant dc reactors recognized the fault. On the other hand, faraway dc reactors did not reach the required Vth,1and/or
Vth,2due to their electrical distance from the fault point.
A PP fault at L24 (0 km from MMC2, location E) is studied as a corner case to evaluate selectivity performance. In this scenario, BRK24 and BRK42 should correctly detect the fault; however, BRK12 might
also mistrip because of the resulting transients from the metallic fault (Rf =0Ω).Table 6offers a summary of the results, showing the peak Dw (referred asDwm) andnthfor all breakers on increasing Rf(0 Ω→250 Ω). It is obvious that only BRK24 and BRK42 correctly detect the fault for all cases (highlighted in orange), and all other breakers will not trip due to lowDw and/or lownth. BRK21 (BRK43) is muted and did not trip anymore (cells in gray), because the sibling breaker BRK24 (BRK42) has already detected the fault.Dwmin some external breakers exceeded EDw but did not have the confirmation fromnth(highlighted in faint blue). The RVCR has resulted in similar results and selected the correct breakers, as shown in the lower half ofTable 6.
6.2.2. Converter internal faults
For a worst-case converter fault, a PP metallic fault at MMC4 is considered (location G in Fig. 1), shorting its positive and negative terminals. The resulting measurements (Dwm andnth) are shown in
Table 7. The data show that theDwm42andDwm43are identical because of MMC4 dc terminals being a common node of D42 and D43. Hence, a fault at MMC4 means the same disturbance is done to measurements
VD42andVD43, making their corresponding RT-BWT wavelet coefficient energies take the same trajectory afterwards (highlighted in green in Table 7). These observations indicate that MMC4 is faulted and BRK4 should be tripped, instead of the other breakers BRK42 and BRK43. This results in less opened breakers and less components absorbing the en-ergy required to break the current, which leads to higher reliability of the dc breaker systems. Furthermore, it correctly allows the healthy dc transmission lines to continue operation, and avoids rerouting of bulk dc currents into other transmission lines which can cause current overload.
The RVCR measured the same tc at D42 and D43, which are con-nected to the faulted MMC4. Furthermore, the VDmvalues are almost equal, which means that the fault must be at the converter level, and the BRK4 is correctly selected for tripping. However, it has falsely de-tected a fault at D31 and D34 on the far end of the connected cables of MMC4, especially in low Rf. The tcat these breakers overlap with the 100 Ω and 250 Ω PG faults [seeTable 5], hence this may cause un-necessary trippings for external breakers. This corner case presents ambiguities for RVCR on whether a transient is caused by an nearby fault or an external (irrelevant) fault. As the RVCR is proposed around the concept of rate-of-change of dc reactor voltage, the results show that thedV
dt
D at an irrelevant MMC fault is higher than thedV dt
D of a
re-levant but high-Rf fault. Hence, this ambiguity will not be easily solved by adjusting the thresholds Vth,1and Vth,2used. On the other hand, the proposed RT-BWT presented its superiority in terms of differentiation between relevant and irrelevant faults.
6.3. Effect of fault event distance
The fault event distance has a similar effect on the resulting tran-sient as the fault resistance. Increasing fault event distance from the sensor means increasing line resistance and capacitance from fault Fig. 10. Effect of Rf, PG fault at L13 (150 km from MMC1): (a) VB, (b) IV, (c) VC,
(d) ID, (e) VD, (f)Dw.
Table 5
origin to the sensor, resulting in more attenuated response. This is evident inFig. 11, which showsVD34andDw34 for a 10 Ω PG fault at different locations along L34, from near D34 (referred as 0 km, location H) to near D43 (450 km, location I). As expected, the voltage across the dc reactor D34 becomes more damped with increasing distance from the fault origin. This, in turn, results in decreasingwD34. On the other hand,VD43transient (not shown infigure) conversely became sharper as the fault location goes nearer MMC4, which resulted in higherD43. However, the effects of fault distance on the resulting Dw is minimal compared to that caused by fault resistance, due to the negligible dc line conductor resistance per km. Therefore, the selectivity and accu-racy of the proposed technique remains unchanged.
6.4. Effect of DC line reactor inductance
DC reactors affect the response in a rather interesting way, because they serve as boundaries between the line- and the bus-side transients. Increasing the dc reactor inductance LDmeans that the transients on one side of the dc reactor are heavilyfiltered when they are measured on the other side, which leads to two consequences. First, higherLD results in higher dc reactor voltages VD, and consequently, higherDw. Second, more filtering brought byLD results in lower VD andDw for external dc reactors. As inTable 8for a 0 Ω PG fault at L12 (150 km from MMC1, location A),Dwrises with increasingLD. Similar with the fault distance, the effect ofLDonwDis only minor compared to when varying Rf. This only shows the consistent performance of the proposed algorithm in terms of identifying the correct breakers to trip, even with different dc reactor sizes. The same was observed after simulating PG faults, in different locations and power flow situations.
6.5. Effect of sampling frequency
The sampling frequency ( fs) is another concern for fault detection methods. The conventional Fourier-based protection methods in ac systems usually use fs =960 Hz. However, the wavelet-based trans-forms need higher sampling frequency for a better detection of
fault-induced high-frequency transients. Fig. 12depicts the effects of the sampling frequency on the performance of RT-BWT. The dc reactor voltage in Fig. 9(a) is analyzed using RT-BWT with sampling fre-quencies of 10 kHz, 5 kHz, and 1 kHz. The RT-BWT wavelet coefficient energies for all the tested frequencies increased to about the same maximum level, but at different rates [Fig. 12]. Therefore, the proposed method presents an advantage in being scarcely affected by the sam-pling frequency. However, higher samsam-pling frequency results in faster reaction to fault transients.
The RT-BWT wavelet coefficient energies have significantly in-creased for all fswith no discrete time delay, meaning that the allDw have spiked at the very next sampling time after the transient arrival. Therefore, the speed of the response is due to the sample timing, as shown in the inset ofFig. 12. While RT-BWT can be implemented on higher sampling frequencies, the RT-BWT already achieved good results and fast performance even with a practically feasible 10 kHz, unlike traveling wave methods which require sampling rates in the MHz range to be effective for dc fault detection purposes[3].
6.6. Effect of noise
The same VD24signal as inFig. 9was used to investigate the noise effects on the resulting RT-BWT wavelet coefficient energies. The re-sultingDw24are shown inFig. 13,first without noise, and adding 35 dB as well as 30 dB SNR white noise[37]. While the peak energies have remained the same, the quiescent values ofwD24 before the fault in-crease with the noise level. This can have effects on the rise rate of RT-BWT coefficient energy (represented bynth), and consequently, on the calibration of the thresholdNth.
6.7. Effect of external AC faults
A 3-phase metallic ac fault was triggered on ac grid 1 (location B), which is a worst-case scenario causing large transients propagating from the ac side of MMC1 to its dc side. All dc and ac breakers are disabled in this scenario in order to let the ac fault transients transfer as Table 6
Effect of dc fault resistance: PP fault on L24 (0 km from MMC2, both Dwmand nthin log10scale) dc line fault detected; muted; no nthconfirmation.
Table 7
much as possible to the dc side. The graphs atFig. 14show that the ac fault resulted to only minor effects on the dc side measurements, in-cluding dc bus voltage, dc line currents, and dc reactor voltage. This relates to the slower ramp-up of the ac-side currents, due to the lumped effect of the interface transformer leakage reactance and the arm re-actors, effectively protecting the submodule switches from overcurrent. Hence, the corresponding wDfor all dc reactors were not enough to trigger the dc fault detection [Fig. 14(f)]. Similar results were achieved on other ac fault locations, higher fault impedances, and phase-to-ground faults. Additionally, other normal operation-related events like converter blocking/deblocking have been tested, and were not mis-recognized as faults.
6.8. Effect of normal operation events
A scheduled converter block is performed for MMC4, as shown in Fig. 15. In this scenario, the breakers BRK42 and BRK43 were muted because this is a scheduled normal operation with respect to the op-erator of MMC4. The operation blocking caused low-frequency tran-sients as sensed by neighboring terminals MMC2 and MMC3 – tran-sients which were outside the passband of the db4 mother wavelet. Hence, there was no significant increase in Dw24andDw34, and did not cause any untoward trippings based on the proposed fault detection.
Step changes in output power were also tested, in which the step changes in output power (for wind-farm side converters MMC2 and MMC4), and power draw (for onshore converters MMC1 and MMC3) were performed. In these tests, no breakers are muted because the step changes are assumed as unscheduled, e.g. activation of a huge load in the ac grid area, or an unexpected increase in wind farm output power. In these cases, the same observations were made with no false detection of the fault due to even less severe transients than in the converter blocking scenario.
7. Fault protection performance with breaker operation
The dc fault studies in the previous section are done without dc breaker operation to characterize the responses ofDwfor the relevant dc reactors and those of the external ones. While this enabled deeper analysis of the effects of Rf, fault distance,LD, and external faults, the effects due to dc breaker tripping operation are not yet considered. Two representative scenarios are discussed in this section to present the proposed protection system with dc breaker operation. Lastly, a sta-tistical evaluation is performed, simulating numerous faults in random Fig. 11. Effect of fault distance, 10 Ω PG fault at L34: (a) VB3, (b) IV3, (c) VC3, (d)
ID34, (e) VD34, (f)Dw34.
Table 8
Effect dc reactor inductance LD: 0 Ω PG fault on L12 (150 km from MMC1, bothDwmand nthin log10scale) dc line fault detected; muted; no nthconfirmation.
Fig. 12. Effect of the sampling frequency on RT-BWT wavelet coefficient en-ergies.
locations, types, and fault resistances, considering dc line faults, con-verter faults, and changes in MTDC grid topology. The statistical tests address the question of accuracy as well as the detection delays with respect to different fault parameters. In all studies presented in this section, the proposed method runs in all four dc buses B1-B4 in-dependently, in order to demonstrate its accuracy and selectivity with no need for communication.
7.1. 0.0 Ω PP fault at L34, 0 km from MMC4
The fault event occurred near B4 (location I), hence the dc link voltage at this bus showed the strongest transients. The results are shown inFig. 16. At the fault instant, the voltage VD43,l(not shown in the graph) plunged immediately to zero. However due to the dc reactor D43, VB4 as shown in Fig. 16(a) only decreased by around 100 kV. Hence, the dc reactor voltageVD43instantly increased to about 500 kV. This caused a sharp spike inDw43andDw42(in the sibling reactor D42, selecting them as candidates for tripping. However, Dw43 was much higher, hence a fault was recognized at line L34, and the trip signal was sent to BRK43. However, the fault current continued to grow to about 6 kA due to the breaker delay. As the main breaker circuit of BRK43 has indeed tripped, the current ID43 has subsided to around zero, which enabled the mechanical breaker to open. As a result of the tripping,VD43 jumped towards around 600 kV. This is because the dc line side of D43 dipped to around 0 kV due to the fault, while the bus B4 stayed at nominal voltage. Similar can be observed forVD34.
The fault transients took about 2.25 ms to travel from the fault origin to the measurement point at B3, thenDw34began to rise. Similar with B4, the fault protection decision unit at B3 recognized two can-didates for breaker tripping, and chose BRK34 for tripping. While BRK34 was starting to open, ID34was changing direction and about to feed the fault. However, the current has crossed 0 kA, leading BRK34 to open without waiting for the full breaker delay. On the other dc buses, Fig. 14. Effect of 3-phase fault at ac grid 1: (a) VB1, (b) IV abc1, , (c) VC1, (d) ID, (e)
VD, (f)Dw.
Fig. 15. Effect of converter blocking of MMC4: (a) VB, (b) ID, (c) VD, (d)Dw.
Fig. 16. 0.0 Ω PP fault at L34 (with dc breaker operation): (a) VB, (b) ID, (c) VD,
no dc breaker tripped due to the non-fulfillment of either or both of the criteria onDwandnth. Hence, the proposed fault protection method has worked perfectly in this case, and the breaker tripping transients from the affected breakers did not adversely affect the measurements at other buses. The detection delay for B4 was less than 50μs, i.e. B4 recognized the fault at veryfirst sample after the fault occurrence, and for B3 it was around 350μs after fault signal arrival at its corresponding sensor.
7.2. 300.0 Ω PG fault at L13, 225 km from MMC1
High-resistance faults prove to be a challenge for fault detection in general because of their resulting damped transients. As shown in Fig. 17for the considered fault at location D, the bus voltagesVB1and
VB3have exhibited very soft response upon arrival of the fault signal on their respective sensors. Moreover, the corresponding changes in the dc currents (ID13andID31) and dc reactor voltages (VD13andVD31) are slow and might be misinterpreted as a non-fault event. However, these transients are still enough for the proposed RT-BWT-based fault pro-tection method to detect. As seen inFig. 17(d), both RT-BWT wavelet coefficient energies wD13 andDw31experienced a sudden rise at about 1.3 ms from the fault event, which fulfilled the criteria on EDwandnth (the twowD13 andDw31overlap in the graph due to the fault location halfway between B1 and B3). Considering the assumed travelling wave speed, the fault transient signal arrived on D13 and D31 sensors at about 1.125 ms after the fault occurrence. Hence, the fault detection was successful within 175μs. Similar to the previous scenario,VD13and
VD31grew starting from the breaker opening time. This is again due to the respective buses B1 and B3 staying at nominal voltage, and the dc side voltages were decreasing due to the fault. However, the line-side voltage decrease is due to high Rf, which means a longer time for the line capacitance to lose its charge. It must be noted that such is the performance of the proposed method, with fs=10kHz, and a high-resistance fault. This only shows the sensitivity of the proposed method even with a relatively low sampling frequency, which makes it
realistically implementable for mid-range or even low-end hardware.
7.3. Statistical analysis
The proposed fault detection scheme was also subjected to a sta-tistical analysis using the test grid, and dc breakers activated. The lo-cations considered are random points along the dc transmission lines, as well as on the converter themselves. The fault resistances are calculated byRf =10 Ωp , where p is a random value from−2.0 to + 2.5, resulting in a range around 0.01–300 Ω with a bias towards low-impedance faults, which are the critical corner cases with risk of misdetection from irrelevant breakers. There are four distinct datasets provided (totalling around 1900 fault scenarios simulated, with half being PP and another half being PG faults), representing different scenarios summarized in Table 9. Two of these test scenarios involve changes in MTDC grid to-pology, which can be due to an outage of a transmission line for maintenance reasons. This way, the robustness of the proposed method and the threshold setting is further evaluated.
7.3.1. On the detection and relevant fault discrimination
A 2D scatter plot is provided inFig. 18, showing the RT-BWT wa-velet coefficient energies Dwin the x-axis, and threshold ratiosnthin the y-axis. For every test case, there are multiple points plotted in the graph, representing individual breaker (BRK12, BRK13, …, BRK43) measurements. Relevant breaker points for each test case are plotted in blue, while irrelevant breaker points are in orange. As an example, for a fault in the middle of L13, points for BRK13 and BRK31 [(wD13,nthD13) and (Dw ,n
thD
31 31)] are plotted as relevant breaker points, and the breakers points from the other MTDC terminals (MMC2 and MMC4) are marked as irrelevant. The sibling breaker points (in the example are BRK12 and BRK34) are not plotted to improve clarity. The markers are plotted by size with the largest being the metallic faults (approaching 0 Ω) and high-Rf faults being smaller.
Fig. 18visualizes how the RT-BWT technique is not fully selective when only measuring theDw, because this will lead to many false po-sitives due to external breakers also reaching the threshold EDw. In terms ofDw, there is a wide overlap between the relevant breakers at high Fig. 17. 300.0 Ω PG fault at L13 (with dc breaker operation): (a) VB, (b) ID, (c)
VD, (d)Dw.
Table 9
Powerflow configurations tested for statistical analysis.
Scenario Pref1 P2 Pref3 P4
S1 −400 MW +350 MW −400 MW +600 MW
S2 −600 MW +700 MW −500 MW +400 MW
S3 Same as S1 but with outage of L12
S4 Same as S2 but with outage of L24
Fig. 18. Statistical test results, differentiation of relevant and irrelevant fault events (both axes in log scale).
resistance faults (smaller blue markers to the center), and the irrelevant breakers at metallic faults (larger orange markers at right-bottom side). Addition of thenthas the confirmation of the fault serves well as a way to further isolate out the external breaker points. This results in a quadrant in the upper-right side that comfortably encloses all the re-levant breaker points, and excludes all the irrere-levant breaker points. This way, the selectivity of the technique is maximized, which results in no unnecessary dc breaker trippings and maintaining the operation of all healthy dc transmission lines.
The observations are consistent even between different power flow situations, as shown by the similar areas occupied by relevant and ir-relevant breaker points for Scenarios S1 and S2. Changes in MTDC to-pology are also investigated, in which it is assumed that L12 (in sce-nario S3) and L24 (in scesce-nario S4) are disconnected due to maintenance. The same statistical tests are performed, which resulted in the same partitions for the relevant faults and irrelevant events, as also shown inFig. 18. This means that the effectiveness of the proposed fault detection mechanism is robust against changes in power flow conditions, and topology changes.
7.3.2. Detection delays
An important criterion for fault protection methods is the detection speed, because it is generally accepted that faster detection results in less power losses when breakers are opened, which in turn leads to less component-level stress.Fig. 19shows the detection delay with respect to Rf and fault distance. This detection delay is calculated as the dif-ference between time of signal arrival and detection time. In the cal-culations, the travelling wave speed along the undersea cable is 2/3 the speed of light. As shown in the results, the detection delay is mostly a function of the distance. This means that nearby faults, whether me-tallic faults or high-resistance faults, are detected with the same short delay in the order of 0.1 ms given fs =10 kHz. As the fault distance increases, the transients arriving at the sensors become more damped and attenuated due to thefiltering action of the cable capacitance along the transmission cable length. This results in a corresponding increase in detection delay, which is found to be around 0.5 ms for faults oc-curring 450 km away. This worst delay from the proposed fault detec-tion technique is, however, shorter than the minimum (best-case) delay required for the method proposed in[13].
7.3.3. Performance limits
There were several observed intersections between relevant high-resistance PG faults at the far end of the line, and the irrelevant corner cases. For example, using the same thresholds as before, BRK34 might not be able to reliably detect PG faults with Rf more than around 300Ω when the fault occurred on the far end of L34. On the other hand,
lowering the thresholds Eth and/orNth to increase the sensitivity to these higher-resistance faults might cause misdetections for a metallic PP fault at MMC4.
As discussed in Section4, the dc fault protection scheme is desired to be sensitive for damped fault transients, and at the same time, reject false detections due to the strongest irrelevant events. Considering this, the proposed fault protection method is found to reliably detect up to about 300Ω (PG) and 750Ω (PP) faults from the far side of the cable, while keeping effective discrimination from the irrelevant corner cases. Higher-resistance faults from the far end might cause skipped detection, i.e. less than 100% detection rate. This observed maximum PG fault resistance for detection is reasonable because the long 450 km cables introduce higher bulk capacitance, introducing damping and attenua-tion to high-resistance fault transients from the far end of the line, especially in PG faults. However, a simple signaling between opposite ends of the line will be able tofill the sensitivity gap. As this signaling is only needed for the high-resistance faults, fault clearing speed is not critical and hence there is aflexibility in choosing the communication technology.
8. Conclusion
This paper presented the use of a simple RT-BWT-based method for real-time dc fault detection and protection in MTDC grids. The pro-posed technique has shown the following advantages:
1. The introduction of the border effects on the wavelet coefficient energy solves the problem of time delays associated with long wa-velets, is more sensitive to transients induced even by high-im-pedance faults, and isflexible in choosing the mother wavelet. 2. The usage of two conditions for fault detection has significantly
increased its reliability, and accuracy. The results have shown that it can choose only the correct breakers, even at corner cases where another technique in the literature has caused misdetections. Furthermore, the performance is still the same even with changed topology and operating points.
3. Its detection speed, selectivity, and sensitivity were verified con-sidering a wide range of internal and external dc faults and MTDC grid events, including the effects of dc fault resistance and distance, smoothing reactor, and sampling frequency.
4. With demonstrated effectiveness even on low frequencies of few kHz and entirely without communications, the proposed RT-BWT method is proven to be viable for practical applications in MTDC grid protection.
An interesting direction for this study is its deployment in a hard-ware-in-the-loop or small-scale laboratory hardware setup. This way, more practical considerations are included, like the effects of voltage measurement discretization due to analog-to-digital converters (ADCs). Identification of the faulted pole in case of PG faults is another inter-esting direction, to make the protection system also appropriate for bipolar MTDC grids. The proposed method is tested in this paper with hybrid dc breakers; however, its effectiveness can also be investigated when integrated with other topologies like fault current limiters. Furthermore, the effectiveness of the RT-BWT for fault detection and protection in LCC-based HVDC networks is interesting to evaluate. These will be investigated in future work.
Declaration of Competing Interest
The authors declared that there is no conflict of interest. Acknowledgements
This work was supported by the Alexander von Humboldt Foundation, the Coordination for the Improvement of Higher Level Fig. 19. Statistical test results, detection delay related to fault resistance and
