Federal University of Rio Grande do Norte Center for Earth and Exact Sciences
Department of Informatics and Applied Mathematics Bachelor in Computer Science
Analysis of routing algorithms for security and
fault-tolerance in NoCs
Hélio Bezerra Duarte Filho
Natal-RN June 2019
Duarte Filho, Hélio Bezerra.
Analysis of routing algorithms for security and fault-tolerance in NoCs / Hélio Bezerra Duarte Filho. - 2019. 51f.: il.
Monografia (Bacharelado em Ciência da Computação)
-Universidade Federal do Rio Grande do Norte, Centro de Ciências Exatas e da Terra, Departamento de Informática e Matemática Aplicada. Natal, 2019.
Orientadora: Monica Magalhães Pereira.
1. Computação - Monografia. 2. Redes em chip - Monografia. 3. Confiabilidade - Monografia. 4. Segurança - Monografia. 5. Roteamento - Monografia. I. Pereira, Monica Magalhães. II. Título.
RN/UF/CCET CDU 004
Universidade Federal do Rio Grande do Norte - UFRN Sistema de Bibliotecas - SISBI
Catalogação de Publicação na Fonte. UFRN - Biblioteca Setorial Prof. Ronaldo Xavier de Arruda - CCET
Hélio Bezerra Duarte Filho
Analysis of routing algorithms for security and
fault-tolerance in NoCs
Undergraduate dissertation submitted to the Deparment of Informatics and Applied Mathematics of the Center for Exact and Earth Sciences of the Federal University of Rio Grande do Norte as a partial require-ment for obtaining the degree of bachelor in Computer Science.
Advisor
Prof. Monica Magalhães Pereira, Ph.D.
Federal University of Rio Grande do Norte – UFRN Department of Informatics and Applied Mathematics – DIMAp
Natal-RN June 2019
Undergraduate dissertation under the title Analysis of routing algorithms for security and fault-tolerance in NoCs presented by Hélio Bezerra Duarte Filho and accepted by the Department of Informatics and Applied Mathematics of the Center for Exact and Earth Sciences of the Federal University of Rio Grande do Norte, being approved by all members of the examining board specified below:
Prof. Monica Magalhães Pereira, Ph.D.
Advisor
Department of Informatics and Applied Mathematics Federal University of Rio Grande do Norte
Prof. Edgard De Faria Corrêa, Ph.D.
Department of Informatics and Applied Mathematics Federal University of Rio Grande do Norte
Prof. Márcio Eduardo Kreutz, Ph.D.
Department of Informatics and Applied Mathematics Federal University of Rio Grande do Norte
Acknowledgements
First of all, I want to thank God that is the author of my life and my savior. To my parents, Hélio and Mara, that are a gift that God gave to me, without their support in every moment of my life, I could never be here. To my brothers, José and Rebeca, for all the support, friendship and affection throughout the years. To my girlfriend Aline, for the support and love over the years.
To my uncles that always supported and believed in me, to my cousins that introduced me to Competitive Programming. To my friends from the university João Victor, André Winston, Matheus Andrade, Geovanni Cassemiro, Raul Silveira, Hiago Mayk, Gustavo Alves and many more. To my friends from Ginga com Tapioca, that trained weekly over years with me, Railton Calheiros and Victor Agnez.
I am also thankful for all the teachers that I had from the first to the last semester. In special to my advisor Prof. Monica that had enough patience with me over the semester and was always open to help me, to all my coaches from ACM ICPC, Carlos Prolo, Rafael Beserra and Sergio Queiroz.
Put your works into the hands of the Lord, and your purposes will be made certain. Proverbs 16:3
Análise de algoritmos de roteamento para segurança e
tolerância a falhas em NoCs
Autor: Hélio Bezerra Duarte Filho Orientador(a): Profa. Dra. Monica Magalhães Pereira
Resumo
Com o passar do tempo as tecnologias de fabricação de chip vão sendo aprimoradas, pos-sibilitando assim uma diminuição no tamanho dos transistores, como previsto por Gordon Moore em 1975. Com a redução do tamanho dos transistores, surgiu a possibilidade de criar sistemas complexos em uma única pastilha, denominados Sistemas em Chip (System on Chip - SoC). Entretanto, aplicações começaram a demandar mais processamento do que o fornecido por SoCs, portanto foi necessário integrar diversas unidades de proces-samento em uma única pastilha, surgindo assim os Sistemas em Chip Multiprocessados (Multiprocessors System on Chip - MPSoCs). Uma das formas mais eficientes de comu-nicação entre os núcleos do MPSoCs é a rede em chip (Network on Chip - NoC), que possui diversas vantagens se comparado a forma mais tradicional de comunicação, por barramento, dentre elas a escalabilidade. Dois aspectos que vem sendo amplamente inves-tigados nas redes em chip são tolerância a falhas e segurança. A tolerância a falhas para redes em chip permite garantir que a rede continue funcionando mesmo que algum com-ponente esteja com falha. Segurança, por sua vez, significa que nenhum software malicioso será capaz de tornar a rede inoperável ou acessar informações que estão sendo trafegadas. Nesse contexto, este trabalho consiste na investigação de algoritmos de roteamento que sejam tolerantes a falhas e garantam algum nível de segurança da rede em chip. Dois algo-ritmos de roteamento foram implementados como estudo de caso e comparados quanto a efetividade em solucionar os dois problemas mencionados. Para isso foi usado o simulador de redes em chip NOXIM e foram realizados testes com partes de aplicações reais para NoCs 4x4 e 5x5.
Analysis of routing algorithms for security and
fault-tolerance in NoCs
Author: Hélio Bezerra Duarte Filho Advisor: Profa. Dra. Monica Magalhães Pereira
Abstract
As time passes the technologies for the fabrication of integrated circuits keeps improv-ing, allowing this way, a reduction in the size of the transistor, as predicted by Gordon Moore in 1975. With the size reduction of the transistor, it emerged a new possibility to create complex systems inside of a single integrated circuit, called System on Chip - SoC. However, applications were requiring more processing capacity than what was given by SoCs, because of this it was necessary to integrate a couple of processing units inside of a single integrated circuit, called Multiprocessors System on Chip - MPSoCs. One of the most effective ways of communication inside of MPSoCs is done using Network on Chip -NoC, it has a lot of advantages if compared with the most common way of communication inside a chip, the bus, one of them is scalability. Two aspects ta has been broadly studied in NoCs are fault tolerance and security. Fault tolerance for NoCs allows to ensure that the network will keep working even if some component fails. Security, specifically, means that no malicious software will be able to turn the network inoperable or access some internal information. In this context, this work consists on the investigation of routing algorithms that are fault tolerant and ensures some security. Two routing algorithms were implemented as case study and compared with relation to the effectiveness of solving the mentioned problems. For this it was used a NoC simulator, NOXIM, and were done tests using real applications for 4x4 and 5x5 NoCs.
List of figures
1 Example of Bus . . . p. 16 2 NoC example . . . p. 17 3 Example of packet . . . p. 18 4 Topologies example . . . p. 18 5 XY algorithm Example . . . p. 28 6 Random XY-YX algorithm Example . . . p. 28 7 Possible path for random XY-YX algorithm . . . p. 29 8 Example of failed router using XY algorithm . . . p. 30 9 Example of heavy traffic and how Buffer XY-YX will deal with it . . . p. 31 10 Possible path for ODD-EVEN algorithm . . . p. 34 11 Scenario A: Example of a 4x4 MPSoC, based on NoC . . . p. 35 12 Scenario B: Example of a 5x5 MPSoC, based on NoC . . . p. 36 13 Example of butterfly traffic . . . p. 37 14 Example of overlap . . . p. 38 15 Random Traffic . . . p. 40 16 Random Traffic with 30% on the same . . . p. 41 17 Random Traffic with 50% on the same . . . p. 41 18 2 paths with overlap . . . p. 42 19 Butterfly Traffic . . . p. 43 20 Random with 50% on the same path and faulty router . . . p. 44 21 Random with Fault . . . p. 44List of algorithms
1 XY algorithm . . . p. 27 2 RANDOM XY-YX algorithm . . . p. 29 3 Buffer based XY-YX algorithm . . . p. 31 4 ODD-EVEN . . . p. 33 5 Random with 30% on the same path generator . . . p. 38
List of Abreviations
BPS - Bits Per Second
MPSoC - Multi Processor System on Chip NoC - Network on Chip
SER - Secured Enhanced Router SoC - System on a Chip
Contents
1 Introduction p. 13
1.1 Work Organization . . . p. 14
2 Theoretical Foundation p. 15
2.1 Types of chips . . . p. 15 2.2 Communication within the chip . . . p. 16 2.2.1 Bus . . . p. 16 2.2.2 Network On Chip . . . p. 16 2.3 Fault Tolerance . . . p. 21 2.4 Security . . . p. 22 3 Prior Work p. 24 3.1 Fault tolerance . . . p. 24 3.2 Security . . . p. 25 4 Algorithms p. 27 4.1 XY . . . p. 27 4.2 Random XY-YX . . . p. 28 4.3 Buffer based XY-YX . . . p. 30 4.4 ODD-EVEN . . . p. 32
5 Results p. 35
5.2 Traffic Patterns . . . p. 36 5.2.1 Random Traffic . . . p. 36 5.2.2 Butterfly Traffic . . . p. 37 5.2.3 2 paths with overlap . . . p. 37 5.2.4 Random with 30% on the same path . . . p. 37 5.2.5 Random with 50% on the same path . . . p. 38 5.2.6 Random with Fault . . . p. 39 5.2.7 Random with 50% on the same path and faulty router . . . p. 39 5.3 Methodology . . . p. 39 5.4 Result Analysis . . . p. 39 5.4.1 Random Traffic . . . p. 39 5.4.2 Random with 30% on the same path . . . p. 40 5.4.3 Random with 50% on the same path . . . p. 40 5.4.4 2 paths with overlap . . . p. 42 5.4.5 Butterfly Traffic . . . p. 42 5.4.6 Random with 50% on the same path and faulty router . . . p. 43 5.4.7 Random with Fault . . . p. 44
6 Final considerations p. 46
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1
Introduction
According to Moore’s law, the number of transistors in a integrated circuit doubles it size every eighteen months period(MACK, 2011). This means that, as time passes the
circuits are increasing in complexity on an exponential rate. A consequence of this law is the possibility to integrate various components in a single chip, also known as integrated systems or SoCs (System-on-chip). If a single chip has multiple cores it is called MPSoC (Multiprocessor System-on-Chip).
As applications became more complex, it demanded faster systems. To solve this necessity, integrated systems with multicore were developed, allowing a single chip to contain hundreds of thousands of integrated cores. With this possibility of integrating cores in one single chip, new challenges emerged.
Until late 1990s, the communication between components in a chip were being done mainly with a bus-bar with point-to-point channels. This communication mechanism is not scalable and has several problems for a large number of components communication. To surpass the problems mentioned before, a new communication mechanism was developed, called switched network. This switched network are also known as Networks-on-Chip (NoCs) (BENINI; MICHELI, 2002).
(TEWKSBURY; UPPULURI; HORNAK, 1992) were the first ones to propose switched networks to communicate components in a integrated system on a single chip. The first experimental solution for this new mechanism of communication was proposed by ( GUER-RIER; GREINER, 1999). The name Network-on-chip was first used by (HEMANI et al., 2000),
and has been broadly accepted by the community.
NoCs have several advantages as scalable bandwidth, short point-to-point connections and communication parallelism. In spite of the disadvantages as high communication latency and high cost, according to (BENINI; MICHELI, 2002), the advantages are much
stronger and the disadvantages will probably be surpassed as the transistor size will become smaller and cheaper.
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A SoC can also be a target for security attacks, using NoC or not, as all computer systems. There are a lot of possible ways to attack a system, one example is to try to degenerate the system, causing it a corruption or denial of service, for example. Other example is to try to extract information of what is in the system, with the objective to stole personal information (ZEFERINO; BARON; WANGHAM, 2014). If the integrated
system uses NoC as the communication infrastructure, the network is the main part of the SoC, because it deals with all the communication done by the system. This means that if it suffers any kind of attack it can destroy completely the SoC or stole everything in it. Because of this, security has a critical importance in a MPSoC based on NoC. The security of the system can be increased implementing mechanisms to block possible attacks(ZEFERINO; BARON; WANGHAM, 2014).
Besides security problems, NoC can have several other problems, related or not with the network structure. With the constant reduction of the size of a transistor, the compo-nents of the NoC are becoming smaller and more susceptible to physical effects. For this reason, NoCs need to be fault-tolerant to guarantee reliability since it deals with all the system information.
The solutions found in literature to cope with both problems are very similar to each other (KHICHAR; CHOUDHARY; MAHAR, 2017) (ZHU; PANDE; GRECU, 2007) (SEPÚLVEDA et al., 2016) (INDRUSIAK; HARBIN; SEPULVEDA, 2017). Based on this, this work proposes a
single solution that can handle both problems, security and fault tolerance. To achieve the purpose of the work, it will be analyzed the solutions for security and for fault-tolerance applied to NoCs and how each solution behaves in case of faults and security attacks, more specifically, time-driven attacks, in the same application. The single solution will be incorporated in a NoC simulation tool and metrics such as latency and packet delivery rate will be evaluated.
1.1 Work Organization
This work is divided in six chapters. The second chapter presents the theoretical foundation to understand the proposed work. The chapter three describes some related work. Chapter four presents the proposed solution, detailing the algorithms selected to solve the problems that were raised in chapter three. Chapter five presents the results and compare with other algorithms from literature. The last chapter provides an overview about the proposed work and experimental results and discusses some future works.
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2
Theoretical Foundation
This chapter presents a solid explanation on the basis to understand the proposed work. It explains the basic concepts about network-on-chip, fault tolerance and security.
2.1 Types of chips
The first basic concept to learn is what is a SoC, it stands for system on a chip, as the name suggests. It means that inside of a single chip there is a variety of components such as memory, processor and others. In order to create a SoC it is required a lot of technology and it was only possible because the constant shortening of the size of the transistor, that nowadays is the basis of all electronic components.
With the advance of technology, parallel computation, this means, breaking the task into multiple smaller ones that can be executed simultaneously, was starting to gain its own space. To support parallel computation, SoCs were not the ideal solution, as it only contains a single processing unit inside the chip. This means that two or more chips are required in order to provide parallel computation. Thus, the communication between tasks can take too much time since it is required an inter-chip communication.
To solve the problem mentioned above, a new technology emerged, the MPSoC, which is a SoC with multiple processing units. The project of MPSoC needs to take in consid-eration a lot of aspects, as cores, memory hierarchy, model of communication, model of programming etc, depending on how each of these aspects will be prioritize, different MP-SoCs will be made. This way the project of MPMP-SoCs is all about trade-off (HILL; MARTY,
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2.2 Communication within the chip
2.2.1 Bus
The bus is the most common communication system model. Bus is also known as shared multi-point architecture. The basic structure of the bus is a channel that all com-ponents of the system are connected and share message through the channel. Figure 1 below shows an example of bus. In figure 1, the circles represents the components such as processor, as it is possible to observe the components are connected through the bus systems, represented by the lines, all components are connected and if a message is sent from one circle all the others can see.
Figure 1: Example of Bus
Source: https://www.gatevidyalay.com/ethernet-bus-topology/
In spite of its widespread use, bus systems presents many issues. For instance, as the number of components inside the integrated circuit grows the delay of delivering message grows in the same proportion, since the bus becomes longer. Another problem of bus system is related to power consumption, since a bus system sends the signals to all connected components. Power consumption also increases as the number of cores increase (CARDOZO, 2005).
2.2.2 Network On Chip
Network on chip (NoC) comes to surpass the problems that bus brings ( SAASTA-MOINEN; SIGUENZA-TORTOSA; NURMI, 2002) (GUERRIER; GREINER, 2000) (JANTSCH et al., 2001). The basic structure of a NoC is a router connected to each component of the
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integrated circuit and also a set of links connecting the routers (ZEFERINO, 2003). One
clear advantage of using NoC is that the communication is separated from the execution. Routers and links are responsible for carrying the information throughout the system and the cores are responsible only for executing the tasks. Figure 2 illustrates a NoC-based MPSoC, where one can see the routers and links connected as a 2D (two dimension) mesh, and the cores connected to the routers.
Figure 2: NoC example
Source: lis.ei.tum.de/en/research/completed-projects/rapidmpsoc
Similar to computer networks, NoCs also communicate using messages (BENINI; MICHELI 2002a). This means that when cores need to exchange information, they send the information in packets to the routers. The routers are responsible for encapsulating the packets inside messages and sending and receiving the messages to one another. The messages travel through links, which are composed by two unidirectional channels, one for each direction. Packets are composed by flits, flits are atomic pieces on link-level that forms a packet, to better understand the concept, figure 3 shows a packet divided into multiple parts, each part is a flit, the header, for example, is a flit. To communicate prop-erly packets need to be sent between routers, from routers to cores and from cores to routers as links only sends flits, packets are divided into flits in a very specific way.
Packets has three main parts, the first one is the header that has all the information about who sends the message, what is the final destination, the size of the message and others. The second part is the proper message that the core is sending. The last part is the terminator that indicates the end of the message. Figure 3 shows an example of packet composed of the three mentioned parts.
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Figure 3: Example of packet
Source: Own authorship
Another important aspect of network on chips is the topology. Topology is the way the routers are physically connected. In this work, it will only be studied mesh topologies, represented on figure 4. More specifically, 2D mesh, illustrated in Figure 2. Figure 4 also illustrates other topologies.
Figure 4: Topologies example
Source: (PHING et al., 2017)
One other important part of a NoC is the flow control. The work of the flow control is to manage the packets that are competing for resources, such as, buffers or links. This way being responsible to avoid starvation and congestion inside the NoC (DOBKIN et al.,
2007).
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when and how the message will be transferred from the entry of a router to one of the exit channels. Switching can be done in two ways, per circuit and per packets. Per circuit, it will close the path from the origin to the destination, so only flits from one message can pass in the path, until the whole packet is delivered. Per packet, messages are divided into smaller parts and send trough different routes. Thus, the complete path does not need to be closed to transfer the packet.
Another aspect that needs to be defined is the routing algorithm. Routing algorithm is the path the packets will take to move between routers. The routing algorithm can make a huge difference in the efficiency of the network. It can also help to surpass a lot of problems, as we will see later in this work. Atagoziyev (2007) defined that routing algorithms can be divided into two categories:
1. Deterministic or Non-adaptive - the route between source and destination does not change. This is the most common way of communication inside a NoC, because of the simplicity of the algorithms and the efficiency. The most common deterministic algorithm is the XY that will be covered later.
2. Non-deterministic or Adaptive - This is the opposite of non-adaptive. The packets or flits from the same pair of source and destination can have different route. This category is divided into two other categories:
(a) Fully adaptive: The algorithm considers all possibilities of routes to be used, even if the packet takes a route that is longer then the optimal.
(b) Partially adaptive: The algorithm only considers a subset of all possible routes. This is also commonly used because it is more flexible than deterministic algo-rithms but less complex than fully adaptive.
Routing algorithms will be the core part of this work so to properly follow the proposed solution it is suggested to review this part whenever is required.
Another aspect of NoCs is the arbitration. Arbitration solves the problem of mutual access to the same resource at the same time inside a NoC (ZEFERINO, 2003). It deals
with internal conflicts to send and receive messages, using a buffer to make messages wait until the router is available to send the packet.
As common networks, NoCs also carries the same problems as deadlocks, starva-tions and livelocks. The concept of this problems are widely used in NoC design and are
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extremely important to deeply understand future concepts. The concepts are presented below:
1. Deadlock - it stands for a cyclic dependency. For instance, assuming that there exists three resources A, B and C. A is waiting for B, B is waiting for C and C is waiting for A. This means that the resources will never stop waiting and the process will be opened forever.
2. Livelock - this happens when the message never reaches its target, for example if a routing algorithm keeps running the packet in a cycle or if it keeps moving away from the target.
3. Starvation - it happens when a message never gets out of a buffer. For example if the arbitration keeps delivering only the message with higher priority, the message of low priority can be waiting forever.
In order to proper evaluate all mentioned aspects that involve a NoC design, there are some basic metrics described bellow :
1. Latency: the time that passed since the message was sent from the source until the moment it reaches the destination. Usually it is calculated as the average between all packets or by the packet that took most time. The time can be calculated as the number of clocks.
2. Number of Hops: the number of links that a packet takes to reach the destination. 3. Throughput: The capacity of information that can go from a router to the other.
Or the maximum number of bits that can be passed in a link by a certain unit of time.
4. Bandwidth: The capacity of information that can pass within the network, or the maximum traffic that the network supports. Usually it is calculated as bits per seconds (bps).
5. Usage fee: The number of channels used divided by the number of total channels. this is a good metric to see if the network needs to be expanded.
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2.3 Fault Tolerance
Fault tolerance is the ability of a system/software to keep working even if some internal component is not working (RANDELL, 1975) (WEBER, 2003).
In literature, one can find many different mechanisms to make systems fault tolerant (VALINATAJ; LILJEBERG; PLOSILA, 2011) (VEIGA; ZEFERINO, 2010) (FOCHI et al., 2015).
In this work it will be explained the ones that are related to the proposed solution. First, it is important to highlight that not all systems needs to be fault-tolerant. Take for example a video game, it does not have the same necessity to be fault tolerant as an airplane. For the purpose of deciding the level of fault tolerance that the system needs to implement there are some common questions that can be done, for example:
1. How critical is the system? 2. How likely is the system to fail?
3. Which type of fault is being addressed?
4. How expensive is it to make the system fault tolerant?
The raised questions help the designers to decide the fault tolerance mechanism ac-cording to the type of fault, such as transient or permanent, and the available budget. Transient faults affect the system temporarily. After an certain period of time, the fault dissipates and the system is back to its normal behavior. On the other hand, permanent faults damage the components permanently. In this case, in order to maintain the sys-tem working, it is necessary either to replace the component or to remove (or isolate) it (DUBROVA, 2013). In this work, it will be addressed only permanent faults since they can
cause a persistent damage to the system. Additionally, the solutions to cope with this type of faults are similar to the ones used in security. Therefore, in order to achieve the main goal of this work, only permanent faults were addressed,
The simplest way to make the system fault tolerant is through redundancy. Redun-dancy means to provide multiple identical instances of the same system and switch to one of the remaining instances in case of a failure. So, for example take an important component of an airplane, the usual approach is to have multiple instances of this same component and once identifying that this one is not working anymore, switch to one of the copies.
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Usually, in order to guarantee fault tolerance the cost of the system will increase. And, even with a fault tolerant mechanism, it is not guaranteed that the system will be available all the time. For this reasons, fault tolerance is applied in the majority of the times just in components that are crucial and can fail easily compared to others in the system. The criteria to decide what component should have redundant instances can follow the same questions proposed for system criteria.
2.4 Security
Security is a vast area in computer science. It is broad and is present in all different parts of the computer and systems. Security is the protection of computer systems from theft or damage to their hardware, software or data (BISHOP, 2003). Not only that but
also to protect for corruption and misdirection to the data and services.
There are many types of security attacks as backdoor, denial-of-service attacks, direct-access attacks and others. Security attacks can be divided into two major parts as follows. 1. Active attacks: An active attack attempts to alter system resources. It modifies the
data or create new data to trick systems.
2. Passive attacks: A passive attack attempts to discover the information from the system but not modify its content. The goal of the attacker is simply to obtain information.
There are many different techniques used to trying to protect the computer/system against attacks. The first way to protect the data is by encrypting it. Encrypting the message is usually done by hashing the content with some function or with the password as the hash (PAAR; PELZL, 2009). A second way to protect the computer is by turning
down the process that is trying to attack the system. This method of protection can be divided in two parts. The first part is to identify that some process is an attacker and the second is to turn this process down. The hardest part of this second approach is actually to identify the threat. If the attacker is just looking the information that is being transmitted, it is really hard to identify the attacker, unless it is delaying the packets to gather the information. Delaying packets is what time-driven attacks makes, in order to obtain information about the packets (SEPULVEDA et al., 2015). This is the type of attack that we will deal latter in this work. There exists many other types of protection
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mechanisms that are not on the scope of this work. However, more information can be found in Baron et al. (2013) and JYV et al. (2018).
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3
Prior Work
This chapter presents previous works that are related to this one divided into two sections, one exposing works related to routing algorithms for fault tolerance and the other one discussing about routing algorithms targeted to enhance security.
3.1 Fault tolerance
In this section, it will be discussed a set of fault tolerant routing algorithms, the algo-rithms that are explained here, were selected to give a better understand on the subject, but not only this, the selected algorithms have a strong relation with the algorithms that will be discussed in the next section.
Li et al. (2009) proposed a fault-tolerant routing algorithm for NoCs. The proposed algorithm is based on dynamic XY routing. The algorithm has the same strategy of dynamic XY when there is no fault in the NoC, this means that it selects the route that is less congested, and, in case of a faulty port, it selects the one that is not faulty. Compared to negative first and DyAD routing algorithms, in the presence of permanent faults, the proposed algorithm can lead to less average packet latency and to less than 20% packet loss rate. (KHICHAR; CHOUDHARY; MAHAR, 2017) proposes a very similar algorithm for
routing that is based on dynamic XY, but also on YX.
In (CHEN et al., 2017), it is proposed a path-diversity-aware fault-tolerant (PDA-FTR)
routing algorithm. The proposed algorithm is based on path diversity information and buffer information, it looks the fault location and the effective buffer length to decide which path to take. The authors compared the proposed solution with Modified X-First and two other adaptive fault-tolerant algorithms. According to the results, PDA-FTR can improve average saturation throughput by 175% with less than 10% of area overhead.
Zhu, Pande e Grecu (2007) introduce and evaluate two different routing algorithms. The first one, called N random walk, sends more than one copy of the packet in the
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network through random paths. The second one is negative first algorithm that can adapt the path in case of the presence of a faulty router. The results shows that N random walk can have the smallest packet loss if the number of copies is as large as 64, but the energy dissipation increases very fast as the number of copies increases.
3.2 Security
This section presents the security algorithms, they were chose because they have a strong relation with the algorithms proposed in the past section and also because they can give a good understanding on how solutions can be done for time-driven attacks.
(SEPULVEDA et al., 2015) proposed a mechanism for NoC protection, in case of
time-driven attacks that contains two main parts. The first part is the random arbitration that pseudo-randomizes which input will be served at the moment. The second part is the adaptive routing that is fully adaptive if the x-coordinate of the destination is greater than the x-coordinate of the current router, if not, it follows west-first algorithm. The proposed mechanism keeps throughput almost constant as attack traffic injection increases, besides having a smaller throughput if a very low traffic injection rate is applied, compared to other deterministic algorithms.
(SEPÚLVEDA et al., 2016) proposed a secured enhanced router (SER) for timing side
channel attack. They proposes an extra hardware part, a global virtual channel control that will determine the number of virtual channels per input. The SER has three stages: allocation, arbitration and switching. SER has a average better throughput as injection rate increases, compared to random arbitration and high priority.
The work presented by (INDRUSIAK; HARBIN; SEPULVEDA, 2017) proposes two
ran-domized algorithms for routing in a Networks-on-Chip, for the problem of side-channel attacks. The first one chooses the routing algorithm between XY and YX, randomly. The second one is based on west-first and it randomizes the turn model routing approaches. The proposed method was tested on a 4x4, 4x3 and 8x8 NoCs. The results shows that, on average, randomization increases the communication latency if compared to fixed XY routing.
(SEPULVEDA et al., 2017) merges routing with secure zone approach to guarantee
security in case of time-driven attacks. The proposed algorithm is called Non-minimal Odd-Even Region-based routing (NOE-RNoC). Sensitive traffic is encapsulated dynami-cally through low-risk paths inside a security zone, in NOE-RNoC. The NOE-RNoC can
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change the secure zone region if some router inside it is been attacked. The algorithm showed a smaller latency as the data injection rate increases, if compared to Hop-based, Exhaustive, Weighted-2D and Bounded. It also showed a 7.2% area overhead and a 5.8% power consumption overhead.
As seen above, time-driven attacks consists on gather information about what is being transmitted inside of the network. The way that the information is obtained is based on the time that a packet will take to go from a router to other, based on this it is possible to discover if the network is full and even some other things, as cache misses and hits.
The nature of the solutions for time-driven attacks and permanent fault tolerance presented in this chapter are very close. The proposed work by this thesis intends to evaluate and create routing algorithms to solve security and fault tolerance problems, using the observation that the proposed solutions for the problems in separate are close to each other. Therefore, a single solution could solve both problems with a simpler algorithm. To do that we will evaluate how the fault tolerance algorithms proposed in this chapter will behave in case of time-drive attacks and vice versa.
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4
Algorithms
In this chapter, it is presented the algorithms investigated in this work. The chapter is structured in sections where each section presents the explanation of the algorithms. In total, four algorithms are compared, two of them are well known algorithms, XY and ODD EVEN, the other two were created inspired in the works of Sepulveda et al. (2015) and Indrusiak, Harbin e Sepulveda (2017), RANDOM XY-YX and BUFFER BASED XY-YX.
4.1 XY
XY is the most common routing algorithm used in NoCs, it is well used because it combines simplicity and an acceptable latency. The algorithm can be defined using the pseudo-code 1.
Algorithm 1 XY algorithm
Input:Coordinate of current and destination routers (curX, curY, destX, destY) Output:Output channel
1 if curX < destX then 2 channel east
3 else if curX > destX then 4 channel west
5 else if curY > destY then 6 channel north
7 else
8 channel south
As can be observed in the pseudo-code 1, the XY algorithm basically defines that if the source and the destination are in different lines and columns, first the packet must go
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to the channels that are in the X direction until it reaches the column of the destination and then goes to the channels in the Y direction (ZEFERINO, 2003). Figure 5 illustrates a
route from router 1 to router 11 using XY routing algorithm. Figure 5: XY algorithm Example
Source: Own authorship
4.2 Random XY-YX
Random XY-YX is an algorithm based on Sepulveda et al. (2015). It is an adaptive algorithm that can pass through all routers which coordinates are within coordinates of source and destination. Therefore, if a packet has been sent from node 1 to 11, it can pass through all red links, in the Figure 6.
Figure 6: Random XY-YX algorithm Example
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The way that Random XY-YX chooses which links will be used is the following: First it will see what are the directions that the packet can make in order to decrease the distance between the current and destination routers. If there are multiple directions, it will choose one randomly. If it has only one possible way, that is the one that the algorithm will take. The pseudo-code is presented in Algorithm 2.
Algorithm 2 RANDOM XY-YX algorithm
Input:Coordinate of current and destination routers (curX, curY, destX, destY) Output:Output channel
1 if curX < destX then 2 channels.push(east)
3 if curX > destX then 4 channels.push(west)
5 if curY > destY then 6 channels.push(north)
7 if curY < destY then 8 channels.push(south)
9 if size(channels) > 0 then
10 channel channels[random()%numberOf(channels)]
An example for a route from router 1 to 11 using Random XY-YX algorithm is illustrated in Figure 7. The chosen route is the one with blue links.
Figure 7: Possible path for random XY-YX algorithm
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The main advantage of this algorithm is the fact that it provides different routes for the same source and destination pair. Thus, if some router fails in the middle of a route, the algorithm is capable of finding an alternative route and bypass the failed router, the algorithm will not solve the problem but will decrease the number of packet that will be lost. Take for example if router 1 is trying to send information to router 11 but router three is not working properly. In the case of classical XY algorithm, the packet will never reach node eleven as shown in figure 8. If the algorithm that is being used is the one presented in this section, the packet can take the same path showed in figure 7 and arrive to the destination properly. One other advantage is that the algorithm will spread the traffic in the network, this way attackers will not discover a lot of things about the network as the delay in their packets will be not so big as it would be in XY, for example, in the case of heavy traffic between overlap routers.
Figure 8: Example of failed router using XY algorithm
Source: Own authorship
4.3 Buffer based XY-YX
The algorithm presented in this section is very similar to the one presented in previous section. The only difference is in the case that the packet has multiple routes to choose. In Buffer based XY-YX, the route that will be chosen is the one that goes to the router with less filled buffer. On the other hand, in Random XY-YX, the route would be chosen randomly.
The routes a packet can take are the same of the previous algorithm. Figure 6 shows one example going from router one to router eleven.
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Algorithm 3 Buffer based XY-YX algorithm
Input:Coordinate of current and destination routers (curX, curY, destX, destY) Output:Output channel
1 if curX < destX then 2 channels.push(east) 3 if curX > destX then 4 channels.push(west)
5 if curY > destY then 6 channels.push(north)
7 if curY < destY then 8 channels.push(south)
9 if numberOf(channels) > 0 then 10 channel channels[0]
11 for i in channels do
12 if bufferLevel(channel) > bufferLevel(channels[i]) then 13 channel channels[i]
This algorithm was initially idealized to solve the problem of faulty routers, and it solves in the same way as RANDOM XY-YX, and also to solve problems if heavy traffic is occurring in a single region of the NoC, as shown in figure 9.
Figure 9: Example of heavy traffic and how Buffer XY-YX will deal with it
Source: Own authorship
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red links are being used as well as routers 5, 6, 7, 9, 10 and 11. If router 1 tries to send information to router 16, the algorithm will identify that the routers’ buffers are heavily filled and will send the packet through the green links in the vast majority of the time. This way not delaying packet so much and making the network supports better time-driven attacks.
This and the past algorithm does not solves the problem of faulty routers or links, it only decrease the number of packets that will be affected by a faulty router or link. The algorithms also do not detect faults, if the decrease of number of lost packets is not sufficient, a mechanism for fault identification must be presented and treated in the NoC.
4.4 ODD-EVEN
The ODD-EVEN algorithm was chose for a comparison purpose with the algorithms presented in sections 4.2 and 4.3, as it can also choose different routes for the same source and destination pair.
The ODD-EVEN algorithm is a well-known algorithm proposed by Chiu (2000). It has been widely used for comparison purpose and has been shown relevant results (ZHANG et al., 2009). In addition, as Chiu (2000) shows, the algorithm is deadlock free.
The ODD-EVEN algorithm is defined by this two theorems:
1. Theorem 1: Packets cannot come from a east direction and goes to a north direction in nodes that are on even columns. Packets cannot come from north direction and goes to west direction, if the node column’s is odd.
2. Theorem 2: Packets cannot come from east direction and go to south in nodes on even columns. Packets are not allowed to come from south and take west direction if the node column’s is odd.
Based on this two theorems the algorithm for odd-even can be observed on algorithm 4, the algorithm can take all the possible paths that will make the distance from the current router to destination closer and that will obey the theorems. Figure 10 illustrates a possible route between router 3 and 9 using ODD-EVEN. The red links highlight the route.
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Algorithm 4 ODD-EVEN
Input:Coordinate of current, destination and source routers (curX, curY, destX, destY, sorX, sorY)
Output:Output channel
1 e0 destX curX 2 e1 (destY curY ) 3 if e0 == 0 then 4 if e1 > 0 then 5 channels.push(north) 6 else 7 channels.push(south) 8 else 9 if e0 > 0 then 10 if e1 == 0 then 11 channels.push(east) 12 else
13 if curX % 2 == 1 || curX == sorX then 14 if e1 > 0 then 15 channels.push(north) 16 else 17 channels.push(south) 18 if destX % 2 == 1 || e0 != 1 then 19 channels.push(east) 20 else 21 channels.push(west) 22 if curX % 2 == 0 then 23 if e1 < 0 then 24 channels.push(south) 25 else 26 channels.push(north)
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Figure 10: Possible path for ODD-EVEN algorithm
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5
Results
This chapter details the simulation results. First, it is described the experiment setup, simulation tool and traffic patterns used as study case. Then average latency results and packet delivery rate are presented.
To evaluate the algorithms, tests were done using two different scenarios considering different NoC dimensions. The first scenario, called scenario A, is composed by a MPSoC based on NoC with 4x4 dimension, resulting in a network with 16 routers. Scenario B uses a 5x5 NoC, i.e. 25 routers in total. Figure 11 and 12 shows both scenarios.
Figure 11: Scenario A: Example of a 4x4 MPSoC, based on NoC
Source: Own authorship
5.1 Noxim and Configurations
The simulator used is Noxim (CATANIA et al., 2015), a well-known simulator that has been widely used (CATANIA et al., 2016) (SALAMAT et al., 2016) (GABIS; KOUDIL, 2016).
It was developed using SystemC, a system description language based on C++. The simulator can give a variety of metrics as average cycle per packet, power consumption, maximum number of cycles to deliver a packet and others. Results can change for each simulation even if the input is the same.
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Figure 12: Scenario B: Example of a 5x5 MPSoC, based on NoC
Source: Own authorship
Basic information about the traffic and NoC are given by a file with extension yaml. Using this file, it is possible to define a lot of parameters about the NoC, for example: mesh dimension, buffer depth, routing algorithm, packet injection rate (pir), traffic distribution, selection strategy, etc.
All tests were done using a GNU G++ compiler, running over a Dell Inspiron 15 series 5000, with a Intel i7 processor 8th generation, base frequency of 1.90 GHz and maximum frequency of 4.80 GHz, 8MB of cache memory and 8GB of DDR5 RAM memory.
5.2 Traffic Patterns
This section aims to explain what traffic patterns were used as study case, as well as explains how they were generated and simulated.
5.2.1 Random Traffic
The first traffic pattern that was tested is random traffic. It is given by the Noxim as a ready to use traffic pattern. The pattern is simply sending packet from a random core to another random core. The number of packets that are injected per second is defined as 0.01 and the probability of retransmission is the same. All of this configurations is done in the configuration file with the yaml extension.
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5.2.2 Butterfly Traffic
Butterfly traffic pattern is also given by the Noxim, and is ready to use. The traffic pattern is better explained visually, because of that, figure 13 explains the pattern. The packet injection rate is 0.01 and the probability of retransmission is also 0.01.
Figure 13: Example of butterfly traffic
Source: Own authorship
5.2.3 2 paths with overlap
This is a traffic pattern created to specifically test the proposed solutions. The basic way that it operates is by choosing two paths that overlaps, with the intention to see how overlap will delay the average time for deliver packets. Simulating this way how a time-driven attack would happen. The transmission needs to be set in a way that using any of the algorithms discussed previously, the paths will have an overlap, to ensure this, input was designed by hand. Figure 14 illustrates an example where routers 1 and 12 are a pair of source and destination, respectively, as well as router 2 and 8. In this example, it is possible to observe that both pairs of source and destination share some routers and links (overlap).
5.2.4 Random with 30% on the same path
This traffic pattern was designed to see how the algorithms deal with high traffic between two fixed routers. It was created to evaluate a possible invader that enters the system and is trying to evaluate the delay in its packets. The code to generate the com-munication was made in C++, generating random pairs of routers to send packets, 30%
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Figure 14: Example of overlap
Source: Own authorship
of this pairs of routers were the same. The pseudo-code 5 describes how the traffic was generated.
Algorithm 5 Random with 30% on the same path generator Input:Size of the mesh: X, Y
Output:List of pair of routers
1 probability 0, 3
2 specialOri random()%(X ⇤ Y )
3 specialDest random()%(X ⇤ Y )
4 answer {}
5 while Number of connections is not enough do
6 if random number from 0 to 1 <= probability then 7 add to answer (specialOri, specialDest)
8 else
9 add to answer (random() % (X*Y), random() % (X*Y))
5.2.5 Random with 50% on the same path
This traffic patter is almost equal the past one except that it generates the same pair of routers half of the time. The code to generate is the same as 5, just changing variable probability to 0,5.
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5.2.6 Random with Fault
This traffic is not given by the NOXIM, it was implemented in C++. As the Random traffic, it generates pair of routers randomly and a random router to fail. Testing how the algorithms will behave in case of fault.
5.2.7 Random with 50% on the same path and faulty router
This traffic was also generated for this work and it is not given by the NOXIM. It acts like random with 50% on the same path, but with a faulty router in the path of the communication that is responsible for 50% of the traffic. The purpose of this test is to simulate an attack and a fault in the same moment.
5.3 Methodology
As NOXIM can give different results for the simulation even if the input parameters are the same and some of the traffics generator is also random, it was necessary to formulate a methodology to test the solutions. For each possible traffic, we simulated in NOXIM 20 times and calculated the average of all the simulations, in the case traffic was given by the simulator. If not, for each generated input we run 20 simulations, with 4 generated inputs and take the average of all of them.
5.4 Result Analysis
In this section, it will be presented the results for each traffic pattern and for each NoC dimension.
5.4.1 Random Traffic
Figure 15 presents the average latency results for all algorithms and the two NoC dimensions using random traffic generated by NOXIM.
As can be seen in 15, for random traffic, all algorithms presented similar average latency results on 4x4, the largest difference was XY is 1.08 times faster than ODD-EVEN NoC. However, algorithms RANDOM XY-YX and BUFFER XY-YX presented an average latency increase of almost 50% on 5x5 NoC, if compared with the 4x4 NoC,
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Figure 15: Random Traffic
Source: Own authorship
for example RANDOM XY-YX is 1.488 times faster in 4x4 if compared with the same algorithm in the 5x5 NoC , the same did not happen with the other two algorithms, the latency on both increased but not as much as on the random and buffer XY-YX. Generating random traffic with a bigger NoC may generate problems as starvation for the here proposed algorithms, this may be the cause of the poor performance on the 5x5 NoC.
5.4.2 Random with 30% on the same path
For this traffic, BUFFER XY-YX presented lower latency in both scenarios. This result was expected because this algorithm can choose different routes for the same pair of source and destination based on the availability of the buffers. Additionally, BUFFER XY-YX also present lower latency than XY and ODD-EVEN. It is important to notice that all algorithms presented approximate latency results, but the algorithms proposed in this work could do better than the others just with 30% of the same communication, on the contrary of random traffic. Figure 16 presents the latency results.
5.4.3 Random with 50% on the same path
Average latency results for this traffic is presented in Figure 17. Based on the results, with half of the traffic between the same pair of routers, the algorithms proposed in this work provided lower latency results than the other two with a great margin. RANDOM
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Figure 16: Random Traffic with 30% on the same
Source: Own authorship
XY-YX is 1.19 times faster than XY and 1.08 faster than ODD-EVEN in 4x4 NoC and 1.35 and 1.23 faster than XY and ODD-EVEN in 5x5 NoC, respectively. The latency results for BUFFER XY-YX shows that this algorithm is 1.20 and 1.09 faster than XY and ODD-EVEN in 4x4 NoC and 1.33 and 1.20 faster than the same algorithms in 5x5 NoC. This result is expected since the RANDOM XY-YX and BUFFER XY-YX were designed to cope with this kind of traffic.
Figure 17: Random Traffic with 50% on the same
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5.4.4 2 paths with overlap
This traffic pattern was created to show demonstrate the potential of RANDOM XY-YX and BUFFER XY-XY-YX. For 4x4 NoC, it happened as expected, and XY, ODD-EVEN had a mean latency of more than 1.5 times of the other two. On the other hand, for the 5x5 mesh, although XY and ODD-EVEN performed worse, the algorithms were not so different of RANDOM XY-YX and BUFFER XY-YX, the exact reason why this happened is unknown but it is reasonable to suspect that the random entries gave nodes that were close, so the RANDOM and BUFFER XY-YX could not spread the traffic, for example if all nodes are on the same line. Figure 18 presents the average latency results for this traffic.
Figure 18: 2 paths with overlap
Source: Own authorship
5.4.5 Butterfly Traffic
This traffic, as the random, showed that for traffics that are more balanced, XY and ODD-EVEN performed better than RANDOM XY-YX and BUFFER XY-YX, as can be observed in Figure 19. ODD-EVEN performed 1.25 times better than BUFFER XY-YX and 1.22 times better than RANDOM XY-YX for 4x4 NoC. This outcome can be explained because RANDOM XY-YX and BUFFER XY-YX keep worse results for traffics that are balanced, this happens because this two algorithms spread the traffic in the network this way causing more packets transitioning in all directions.
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Figure 19: Butterfly Traffic
Source: Own authorship
5.4.6 Random with 50% on the same path and faulty router
Traffics with faulty routers were analyzed over a different optic, not about latency but about the rate of packets received over packets sent. Figure 20 presents the result on delivered packets rate. In random with 50% on the same path, RANDOM XY-YX delivered 1.76 times more packets than XY and 1.71 times more packets than ODD-EVEN for 4x4 NoC and, 1.91 times more packet than XY and 1.53 times more packets than ODD-EVEN for 5x5 NoC. Comparing RANDOM XY-YX with BUFFER XY-YX, RANDOM was better 1.04 times for 4x4 NoC and BUFFER was better 1.08 times for 5x5, showing that they are almost equivalent.
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Figure 20: Random with 50% on the same path and faulty router
Source: Own authorship
5.4.7 Random with Fault
Finally, Figure 21 presents the delivered packet rate results for the last traffic. Figure 21: Random with Fault
Source: Own authorship
Random with faults showed a much more consistent result over all the algorithms and also over all the different sizes of meshes, for the 4x4 Noc the biggest difference was between BUFFER XY-YX and ODD-EVEN, BUFFER XY-YX delivered 1.08 times more packets, for 5x5 NoCs, XY was 1.14 times better than RANDOM XY-YX, consisting on
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the biggest difference, showing that all results were almost the same. This is expected since all the traffic was generated randomly so even if one router is not working in the center of the network, the load is well balanced over the whole network, and the location of the fault did not make much difference.
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6
Final considerations
This work presented an investigation on routing algorithms for Network-on-Chip to cope with faulty routers and time-driven attacks. Since the solutions presented in literature to cope with each problem individually are very similar, this work attempted to cope with both problems with one single solution.
In order to handle permanent faulty routers and time-driven attacks, two algorithms were proposed, inspired by the ones found in literature, called RANDOM XY-YX and BUFFER XY-YX. The algorithms were implemented in a NoC simulation tool and com-pared with two other widely known algorithms, XY and ODD-EVEN.
The main metrics used to measure the algorithms were the latency and the rate of packets delivered over packets sent, for the case of faulty routers in the network.
Based on the results, it is was possible to conclude that the proposed algorithms presented better results than the ones widely used in literature, in many of the study cases. The main difference between the results can be observed at the traffic patterns that distributes the packet in a non-balanced way, for example RANDOM XY-YX is 1.19 times faster than XY and 1.08 faster than ODD-EVEN in 4x4 NoC and 1.35 and 1.23 faster than XY and ODD-EVEN in 5x5 NoC, respectively, in the case of half of the traffic communication is the same pair of routers, and the other half is random. In case of balanced injection of the packets in the network, the well-known algorithms were slightly better, but overall the results were almost the same for 4x4 NoC, take for example the case where the traffic is completely random, the largest difference was between XY and ODD-EVEN with the XY being 1.08 times faster than ODD-EVEN. In spite of that, when considered a larger NoC, the proposed algorithms did not perform well, loosing a lot of the benefits even when the study case considered traffics that should favor the proposed algorithms, for example for 2 path with overlap, BUFFER XY-YX was more than 1.5 times faster than ODD-EVEN in the 4x4 NoC, but for 5x5, BUFFER XY-YX was only 1.15 times faster.
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Future works include a deeper investigation on the results, to understand why some results were not as expected; simulate traffic in larger NoCs and add different traffic patterns, with different injection rates. In an attempt to find more efficient algorithms, it is possible to try to analyze a moment to shut down routers, when it is causing a perturbation or increasing the average latency more than expected. Also analyzing different adaptive algorithms in the literature can be used to give a better understanding in the expected output for the traffic patterns.
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References
ATAGOZIYEV, M. Routing algorithms for on chip networks. Master of Science Thesis, The graduate school of natural and applied sciences, 2007.
BARON, S. et al. Segurança em redes-em-chip: mecanismos para proteger a rede socin contra ataques de negação de serviço. Universidade do Vale do Itajaí, 2013.
BENINI, L.; MICHELI, G. D. Networks on chips: A new soc paradigm. Computer-IEEE Computer Society-, Institute of Electrical and Electronics Engineers, v. 35, n.
EPFL-ARTICLE-165542, p. 70–78, 2002.
BISHOP, M. What is computer security? IEEE Security & Privacy, IEEE, v. 99, n. 1, p. 67–69, 2003.
CARDOZO, R. da S. Redes-em-chip de baixo custo. Master’s Thesis, Instituto de Informática-Universidade Federal do Rio Grande do Sul, Porto Alegre, RS, Brasil, 2005. CATANIA, V. et al. Noxim: An open, extensible and cycle-accurate network on chip simulator. In: IEEE. 2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP). [S.l.], 2015. p. 162–163.
CATANIA, V. et al. Cycle-accurate network on chip simulation with noxim. ACM Transactions on Modeling and Computer Simulation (TOMACS), ACM, v. 27, n. 1, p. 4, 2016.
CHEN, Y.-Y. et al. Path-diversity-aware fault-tolerant routing algorithm for network-on-chip systems. IEEE Transactions on Parallel and Distributed Systems, IEEE, v. 28, n. 3, p. 838–849, 2017.
CHIU, G.-M. The odd-even turn model for adaptive routing. IEEE Transactions on parallel and distributed systems, IEEE, v. 11, n. 7, p. 729–738, 2000.
DOBKIN, R. R. et al. Credit-based communication in nocs. Lecture on Introduction to Networks on Chips: VLSI Aspects, 2007.[Online], Citeseer, 2007.
DUBROVA, E. Fault-tolerant design. [S.l.]: Springer, 2013.
FOCHI, V. M. et al. Técnicas de tolerância a falhas aplicadas a redes intra-chip. Pontifícia Universidade Católica do Rio Grande do Sul, 2015.
GABIS, A. B.; KOUDIL, M. Noc routing protocols–objective-based classification. Journal of Systems Architecture, Elsevier, v. 66, p. 14–32, 2016.
GUERRIER, P.; GREINER, A. A scalable architecture for system-on-chip
interconnections. In: Sophia Antipolis Forum on MicroElectronics (SAME’99). [S.l.: s.n.], 1999. p. 90–93.
49
GUERRIER, P.; GREINER, A. A Generic Architecture for on-Chip Packet-Switched Interconnections. DATE’2000. [S.l.]: IEEE Press, Piscataway, 2000.
HEMANI, A. et al. Network on chip: An architecture for billion transistor era. In: Proceeding of the IEEE NorChip Conference. [S.l.: s.n.], 2000. v. 31, p. 11.
HILL, M. D.; MARTY, M. R. Amdahl’s law in the multicore era. Computer, IEEE, v. 41, n. 7, p. 33–38, 2008.
INDRUSIAK, L. S.; HARBIN, J.; SEPULVEDA, M. J. Side-channel attack resilience through route randomisation in secure real-time networks-on-chip. In: IEEE.
Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2017 12th International Symposium on. [S.l.], 2017. p. 1–8.
JANTSCH, A. et al. Networks on chip. In: Workshop at the European Solid State Circuits Conference. [S.l.: s.n.], 2001.
JYV, M. K. et al. Run time mitigation of performance degradation hardware trojan attacks in network on chip. In: IEEE. 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). [S.l.], 2018. p. 738–743.
KHICHAR, J.; CHOUDHARY, S.; MAHAR, R. Fault tolerant dynamic xy-yx routing algorithm for network on-chip architecture. In: IEEE. Intelligent Computing and Control (I2C2), 2017 International Conference on. [S.l.], 2017. p. 1–6.
LI, X. et al. Fault-tolerant routing algorithm for network-on-chip based on dynamic xy routing. Wuhan University Journal of Natural Sciences, Springer, v. 14, n. 4, p. 343–348, 2009.
MACK, C. A. Fifty years of moore’s law. IEEE Transactions on semiconductor manufacturing, IEEE, v. 24, n. 2, p. 202–207, 2011.
PAAR, C.; PELZL, J. Understanding cryptography: a textbook for students and practitioners. [S.l.]: Springer Science & Business Media, 2009.
PHING, N. Y. et al. Topology design of extended torus and ring for low latency network-on-chip architecture. Telecommunication Computing Electronics and Control, v. 15, n. 2, p. 869–876, 2017.
RANDELL, B. System structure for software fault tolerance. Ieee transactions on software engineering, IEEE, n. 2, p. 220–232, 1975.
SAASTAMOINEN, I.; SIGUENZA-TORTOSA, D.; NURMI, J. Interconnect ip node for future system-on-chip designs. In: IEEE. Proceedings First IEEE International Workshop on Electronic Design, Test and Applications’ 2002. [S.l.], 2002. p. 116–120.
SALAMAT, R. et al. A resilient routing algorithm with formal reliability analysis for partially connected 3d-nocs. IEEE Transactions on Computers, IEEE, v. 65, n. 11, p. 3265–3279, 2016.
SEPULVEDA, J. et al. A security-aware routing implementation for dynamic data protection in zone-based mpsoc. In: ACM. Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands. [S.l.], 2017. p. 59–64.
50
SEPÚLVEDA, J. et al. Dynamic noc buffer allocation for mpsoc timing side channel attack protection. In: IEEE. Circuits & Systems (LASCAS), 2016 IEEE 7th Latin American Symposium on. [S.l.], 2016. p. 91–94.
SEPULVEDA, M. J. et al. Noc-based protection for soc time-driven attacks. IEEE Embedded Systems Letters, IEEE, v. 7, n. 1, p. 7–10, 2015.
TEWKSBURY, S.; UPPULURI, M.; HORNAK, L. Interconnections/micro-networks for integrated microelectronics. In: IEEE. Global Telecommunications Conference, 1992. Conference Record., GLOBECOM’92. Communication for Global Users., IEEE. [S.l.], 1992. p. 180–186.
VALINATAJ, M.; LILJEBERG, P.; PLOSILA, J. A fault-tolerant and hierarchical routing algorithm for noc architectures. In: IEEE. 2011 NORCHIP. [S.l.], 2011. p. 1–6. VEIGA, F.; ZEFERINO, C. A. Implementation of techniques for fault tolerance in a network-on-chip. In: IEEE. 2010 11th Symposium on Computing Systems. [S.l.], 2010. p. 80–87.
WEBER, T. S. Tolerância a falhas: conceitos e exemplos. Apostila do Programa de Pós-Graduação–Instituto de Informática-UFRGS. Porto Alegre, p. 24, 2003.
ZEFERINO, C. A. Introdução às redes-em-chip. V Escola de Microeletrônica Sul (livro texto). Porto Alegre: SBC, p. 93–104, 2003.
ZEFERINO, C. A.; BARON, S.; WANGHAM, M. S. Segurança em redes-em-chip: Conceitos e revisão do estado da arte. RITA, v. 21, p. 110–126, 2014.
ZHANG, W. et al. Comparison research between xy and odd-even routing algorithm of a 2-dimension 3x3 mesh topology network-on-chip. In: IEEE. 2009 WRI Global Congress on Intelligent Systems. [S.l.], 2009. v. 3, p. 329–333.
ZHU, H.; PANDE, P. P.; GRECU, C. Performance evaluation of adaptive routing algorithms for achieving fault tolerance in noc fabrics. In: IEEE. Application-specific Systems, Architectures and Processors, 2007. ASAP. IEEE International Conf. on. [S.l.], 2007. p. 42–47.
