Tens Picosenconds Digital ASIC Time To Digital Converter for
Phisics Experiments stefano russo
LPNHE, Electronics group 9/03/2012
Outline
- Why a time measure?
- Different TDCs
- The TEMPO TDC
- A first version @ 180nm
- The final chip @ 90nm
Why a time measure?
Time To Digital Converters (TDC) are widely used in many different fields
Physics experiments
• Time Of Flight
• Positron Emission Tomography (PET)
• Laser applications
…
Applied Electronics
• All digital frequency synthesis
• GFSK transceivers (frequency
modulators)
• On chip test structures
…
All Digital TDC
Many different schemes to implement a TDC (both analogic and digital)
Digital Scheme
• More performances on Avaliable Technologies
• Easy to port design in different tech
• Performances scale almost linearly with tech
How to design a TDC
To have a good resolution on a wide dynamic range a synchronous counter and asynchronous
fine interpolator are realized
Course measure (sync)
fine measure (async)
The fine measure
There are many different schemes to design the fine interpolator
Vernier Based
The time interval is compared to a fixed time
scale (like a caliper)
Direct Measure
The time interval in measured in terms of a
fixed quantity (like a meter)
Vernier Based design examples
Resolution is |τ2-τ1|
τ2 ≠ τ1
TLtH ≠ THtL
…
…
Direct Measure design
Resolution = tinv
Which inverter?
In a direct measure scheme the inverter design is the key element to achieve a good resolution
CMOS inverter (static)
The inverter delay optimization is a tradeoff between:
- MOS dimensions
- parasitic C
- rise fall time
Which inverter?
NORA inverter (dynamic)
The inverter needs a precharge signal
(PRE) to be activated.
The output is valid after the signal EVAL
N type Inverter P type Inverter
OUTPUT N PRE N
INPUT N
EVAL N
OUTPUT P INPUT P
PRE P EVAL P
NORA Logic pros & cons
PRO
- speed (Eval parasites are not on the signal path)
- TH2L ≠ TL2H
CONs
- Many signals
- TH2L ≠ TL2H N type Inverter
OUTPUT N PRE N
INPUT N
EVAL N
P type Inverter
OUTPUT P INPUT P
PRE P EVAL P
NORA vs. CMOS
To evaluate the performances a comparative simulations was performed @ 180nm
…
0 0.5 1 1.5
0 1 2
ns
StartCMOSNORA
0 0.5 1 1.5
0 1 2
ns
0 0.5 1 1.5
0 1 2
ns 1.17 ns
0.77 ns
3rd inverter 37th inverter
NORA is Faster 34%
than CMOS
The TEMPO scheme
Inverters in the fine interpolator are
designed using NORA logic
D Q D Q
D Q
Start
Stop
synchronous counter Start
Stop
N P P
• High resolution
• Reduced dead time
• Low power
The TEMPO scheme
A first chip @ 180nm (UMC)
To validate our scheme a first version was realized
TDC1 TDC2
Full custom design for delay lines
TDC1 measure the time between START
& Stop
TDC2 measure a clock period
(calibration)
A first chip @ 180nm Experimental Results
Resolution = 41 ps on 18 μs range
11 11.5 12 12.5 13
0 20 40 60
measured time (ns)
fine interpolator output
A first chip @ 180nm Experimental Results
Max Differential Non Linearity
0.35 LSB
0 10 20 30 40 50 60
-0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4
fine interpolator output
DNL(LSB)
0 10 20 30 40 50 60
-0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8
fine interpolator output
INL(LSB)
Max Integral Non Linearity
0.75 LSB
A first chip @ 180nm Experimental Results
Single shot precision histograms
117 118 119 120 121 122 123
0 200 400 600 800 1000 1200 1400 1600 1800 2000
result of the measure
number of hits 5ns
41 hits
237 238 239 240 241 242 243
0 200 400 600 800 1000 1200 1400 1600 1800 2000
result of the measure
number of hits
10ns
168 hits
467 468 469 470 471 472 473
0 500 1000 1500 2000 2500
result of the measure
number of hits 20ns
929 930 931 932 933 934 935
0 200 400 600 800 1000 1200 1400 1600 1800
result of the measure
number of hits 40ns
a) b)
c) d)
A first chip @ 180nm Experimental Results
Single shot precision temperature dependence
0 10ns 20ns 30ns 40ns 50ns 60ns 70ns
0 500 1000 1500
measured time
taps
NORA vs. CMOS @ 90nm
…
NORA is Faster 29%
than CMOS
The TEMPO Differential scheme
The delay element compute two differential outputs.
The output is stabilized by the latch and acquired by a Strong Arm FF
A second chip @ 90nm (UMC)
In the second chip the differential scheme was implemented
Full custom design for delay lines
TDC1 measure the time between START
& Stop
TDC2 measure a clock period
(calibration)
Measured resolution 25 ps over 10.6 μs
A second chip @ 90nm Experimental Results
Max Differential Non Linearity
0.35 LSB
Max Integral Non Linearity
0.65 LSB
Experimental Results Summary
Technology Resolution Range Area Power INL DNL
180nm 41ps 18μs 0.09mm 25mW 0.77LSB 0.35LSB
90nm 25ps 10.6μs 0.1mm 19mW 0.65LSB 0.35LSB
