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3.2 Digital Filter
3.2.1 Digital Filter Higher Level Design for the FPGA
The band pass filter to be projected has a pass band from 50 MHz to 70 MHz with a maximum attenuation of 3dB and has attenuation bands bellow 45 MHz (inclusive) and above 75MHz (inclusive) with a minimum attenuation of 80 dB.
From here on, the attenuation in the pass band will be designated by and the attenuation in the rejection band will be referred by .
For the required filter’s implementation it is proposed the use of a FPGA of the family Spartan 3A by Xilinx. This family presents DSP slices that work at 250 MHz, each of which contains a multiplier of 18x18 bits, a pre adder of 18 bits and an accumulator of 48 bits. The differential Input/Ouput ports run slightly above 640 Mb/s. Because the DSP slices have parallel buses at their entrance, the minimum I/O rate demanded is 250 Mb/s.
The most complex XC3SD3400A device of Spartan 3A family was picked. It has 126 DSP slices, 373 Kb of distributed RAM and a total block RAM of 2268 Kb. It comprises 309 I/O ports which is quite above the minimum sought of 12. [31], [32]
It will be seen later, the minimum number of DSP slices needed is 73+41=114 with pre adder or 146 + 41 = 187 DSP slices without pre-adder. Since a pre-adder exists, the minimum number of DSP slices necessary in the FPGA is exceeded.
Other FPGA families were considered. The second best option, found for use, is the Virtex 6 device, XC6VLX75T [34]. This family presents DSP slices with much better specifications but which clearly exceed the requirements. For this reason, this last device was not our first option.
It was considered that all the inputs of the FPGA are samples with magnitude between 0 and 1. It is noted that it is possible to normalize any filter entries to a value in this range knowing the maximum absolute value of the samples that arrive to the filter. Thus it was inserted the following data in FDATool (Filter Design Analysis Tool), a tool from the Matlab (Matrix Laboratory) software that allows the simulation of digital filters [35]:
The inputs and outputs of the filter have 18 bits and the coefficients are also represented with 18 bits.
The output of the multiplier is constituted of 36 bits (18 + 18) and lastly the accumulator has a capacity for storing 48 bits.
In the next 3 sub sections, all the possible digital filter high level architectures that can accomplish the digital filter sought will be compared. First, FIR filters will be addressed and then IIR filters will be discussed. Finally, the filter to be implemented will be briefly discussed.
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Filter Type [dB] [dB] Order
Equiripple 3 87 116
Equiripple 1 86 135
Generalized Equiripple 3 84 120
Generalized Equiripple 1 84 145
Table 3.3 – Characteristics of minimum order FIR filters that meet the specifications (80 dB attenuation in the quantized coefficients’ filter), obtained through Equiripple methods simulated using FDATool.
Figure 3.2 – Magnitude response of Equiripple solution with = 1 exposed in Table 3.3.
Note that the difference in attenuation between the reference coefficients response and the 18 bits quantized coefficients response is negligible. The difference is 1 dB attenuation maximum.
Analyzing Table 3.3, it is observed that the act of reducing to 1 dB, improving the filter bandpass response, requires more coefficients. In this case, additional 19 to 25 coefficients are needed depending on the chosen solution. Results have shown that the Equiripple method spares between 4 and 10 coefficients with respect to the Generalized Equiripple solution.
Another option is resorting to window techniques, once more considering = 3 , but now when applied to 50 MHz and to 70 MHz. This happens because unlike the Equiripple techniques that produce ripple in the pass band, the windows method does not generate that ripple, so the filters obtained can attenuate up to 3 dB in the extremes of the pass band.
In Table 3.4, the results for those windows which allow us to meet the filter requirements are presented. This procedure produces filters that have a magnitude response dependent on the window chosen. Usually the attenuation band is composed by sidelobes. Most often, these do not have a constant amplitude.
Window [MHz] [MHz] Additional data Order
Chebyshev 49 71 SA* = 82 230
Nutall 49 71 X 215
Blackman Harris 49 71 X 220
Gaussian 49 71 α = 3,4 285
Flat Top 49 71 X 275
Table 3.4 – Characteristics of minimum order FIR filters that meet the requirements using windows. These results were obtained with FDATool. *SA – Sidelobe attenuation [dB]
It can be seen in table 3.4, that, to make it possible for the filter’s attenuation to reach 80 dB in
the 5 MHz frequency span of the transition bands, it is necessary a large number of coefficients relatively to the Equirriple methods. This happens in all the cases presented in
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Table 3.4. To note that in the case of FIR filters, the number of coefficients corresponds to the order of the filter added to one.
All FIR filters showed on Tables 3.3 and 3.4, have linear phase response. This implies a constant phase delay, however, because of all the analog filters in the LTE filter chain, this is rather irrelevant, as the total phase response of the LTE filter is very unlikely to be linear.
In the filter design, it is intended to reduce the number of filter coefficients, respecting, although, all the specifications of the filter, because that will reduce the filters latency and diminish the hardware required to implement it. Note that the number of coefficients is directly linked to the exact number of DSP slices necessary to implement the digital filter, the first block inside the FPGA. In this way, the main conclusion to take so far is that in the FIR filter case, the Equiripple method with = 3 is the one that minimizes the number of DSP slices required, making the digital filter more reliable. However, the Equiripple method with = 1 solution would, on the other hand, produce less ripple in the passband, and even taking into account the equalizer that follows in the FPGA, the total ripple produced in the whole LTE filter is significantly reduced if = 1 . Because of this improvement in the smoothness of the power magnitude of the signal in the passband, this is the solution to choose so far.
Finally, it is relevant to state that if the coefficient quantization was done with 25 bits instead of 18, using the equiripple method and = 1 there would be an order reduction of 2 (attenuation required would be 2 dB lower, of 84 dB which gives an order of 132) to achieve the same quality of digital filtering. This proves the advantage in utilizing 25 bits coefficients instead of 18 bit coefficients, is in this case, very small. (There are other FPGAs that have DSP slices with 18x25 multipliers).
The IIR filters option was also studied. That study is shown in the appendix, section 3.3. In practice, IIR’s are usually only used with order up to 8. The reason is the complexity of the filters and their possible instability allied to the fact that a non linear phase response makes these solutions unattractive compared to using FIR filters.
It can be found, observing Table a3.1 in the appendix, section 3.4, that the minimum order for an IIR filter to successfully comply with the requirements, is, in this case, order 12, which is considerably high.
The Equirriple method with = 1 does seem the best option so far, however it turns out not to be that way. This is because the coefficients are quantized with 18 bits, and so they have minimum resolution of 2 ≅7.63 . Two of the coefficients obtained with this solution have lower values than this and will be quantized to 0 which will induce an error in the FIR calculations. Because of this, the Generalized Equirriple solution with = 1 was selected. (It is also important that the order of the filter obtained is odd, because that allows us to spare half the amount of DSP slices used for its implementation, but that also happens in the Equiripple solution with the same value of ).
The main conclusion to take from the above results, is that FIR filters, more specifically, the Generalized Equiripple method with = 1 presents the most promising solution for the designing the filter specified.
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The filter to be implemented is therefore a FIR, projected with a Generalized Equiripple technique with
= 1 . It has an order of 145 which means it has 146 coefficients and will require the use of 73 DSP slices to be accomplished. This will be verified later.
3.2.2 Digital Filter Lower Level Design for the FPGA
The general FIR filter equation is a summation of products as represented in expression 1:
= ℎ (3.5)
There are several different digital circuits that can make this computation. They all have different strengths and weaknesses and all will be studied so that the circuit that best meets our purposes can be selected. There are serial FIRs, parallel FIRs which separate into 2 categories, transposed and systolic filters and finally there are semi-parallel FIRs. [36]
An example of a serial FIR and an example of a transposed FIR can be viewed in the appendix, section 3.4. The architectures selected are presented ahead.