Low Pass Filter
3. FPGA Block
3.1 Introduction
The general architecture of the FPGA block is illustrated in figure 3.1.
Figure 3.1 – Internal constitution of the FPGA block.
The FPGA block behavior is now briefly explained. In order to take advantage of the full capabilities of the analog to digital converter selected, the voltage of the signal at its input must cover the full range of the ADC or as much close to it as possible. For that purpose a voltage level adapter is employed before the ADC.
Next, the signal enters the FPGA as a bitstream composed of 16 bit words in rapid series. These represent the signal values that are digitally encoded. The digital signal, first of all, passes through a FIR (Finite Impulse Response) Digital Filter that is basically a digital band pass filter which achieves the 80 dB attenuation in 5MHZ transition bands on both sides of the pass band. Afterwards the signal traverses an equalizer. The signal hereafter leaves the FPGA and arrives the DAC (digital to analog converter) where it is then again converted to an analog signal. Lastly there is a power level adapter so that the signal that enters the Upconversion block, has the highest possible power while respecting the minimum safety margin from saturating the first mixer ahead.
3.2 ADC
The ENOB specifies the number of bits in the digitalized signal above the noise floor. [25]
= [ ]−1.76
6.02 (3.1) Where SINAD is defined as:
= + =
+ (3.2)
For a more detailed explanation of the SINAD parameter, consult the appendix, section 3.1.
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All real components operate under a certain amount of noise. If the converter has a sufficient resolution to represent signal levels below the system noise floor, the lower bits of the digitalized signal only represent system noise and do not contain useful information. ENOB specifies the number of bits in the digitalized signal above the noise floor of the ADC.
This will be the main parameter used to select an ADC and to simulate it. A device with the biggest ENOB possible will be chosen taking into consideration that the FPGA used after the ADC accepts up to 18 bits. The error introduced by the ADC can simply be the error introduced by quantizing an analog signal with the ENOB number of bits. However, this only happens if the other errors introduced by the ADC operation only affect bits that are less significant than the ENOB more significant ones.
Another restriction in the ADC to be used is its minimum working rate, because the analog signal must be sampled at a rate high enough so it can be digitalized and reconstituted in the analog domain without any loss of information and a very small error introduced.
It is known that, to avoid aliasing, a band pass signal with centre frequency and bandwidth Δf must be sampled at a frequency which meets the following specification [26], [27]:
2 + Δf
2 ≤ ≤ 2
−1 − Δf
2 , ≥1 ⇔ (3.3)
⇔ 2
≤ ≤ 2
−1 , ≥1 (3.4) A compromise must now be reached. There are two variables in equation (9), and .
A higher means the replicas are more apart (Refer to figures 17 and 18) from each other and the digitalization will be of better quality. At the same time, it also means the speed of processing of the FPGA ahead and the DAC that follows must be higher. A lower brings the possibility that a FIR digital filter with a lower order will be able to address the specifications demanded.
The quality of the AD conversion was favored instead of the lower processing speed and lower order of the digital filter. First, was maximized according to the speed of ADC processing existent on the market. Care was taken to also obtain the highest ENOB and the smallest introduced error in the conversion as possible. has a value of 250 MHz. Next, was chosen. The goal was to increase as much as feasible, the frequency gap between the replicas.
We want to call the attention to the fact that several different ADCs’ were researched, through their datasheets. Of all those, the AD9446 from Analog devices, was the one with the highest ENOB, with a value of 12.9 at 70 MHz. It had 16 bits resolution and worked at 80 MSPS or 100 MSPS.
The ADC chosen was, however, the AD9467 from the Analog Devices corporation. This was the industry’s fastest 16 bit ADC, running at 250 MSPS at the date of 27 September 2010. [28]
Its specifications are represented in table 3.1. There are some parameters in that table that require an explanation. Those explanations, which are related with the ADC operating principles are given in the appendix, section 3.1. [25]
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Table 3.1 – Most important specifications of the chosen ADC including noise and distortion but excluding error specifications [29]
The 4 types of error of an ADC are discussed in the appendix, section 3.2.
The specifications of these 4 error types for the ADC to be used, are exhibited in table 3.2. [30]
AD 9467 Minimum Typical Maximum
Offset Error - 150 LSB 0 LSB 150 LSB
Gain Error - 3.5 %FSR - 0.1 %FSR + 2.5% FSR
DNL Error - 0.6 LSB ∓ 0.5 LSB +1.3 LSB
INL Error - 11.8 LSB ∓ 3.5 LSB + 9.5 LSB
Table 3.2 – Error specifications of the chosen ADC.
The typical gain error will need to be compensated. This is because in a full scale of 2.5 V, 0.1% is equivalent to 65.536 LSB ( = = 65.536 ) . This affects up to the lower 7 bits of the codeword which is unacceptable because it reduces far too much the quality of the digitalization process.
Minimum and maximum offset and gain errors shall be corrected only if their occurrence is not sufficiently rare. These problems are, as discussed in the appendix, addressable, and therefore, do not impose an impairment on the ADC performance.
The SFDR is a worst case harmonic characterization parameter. The SFDR of the chosen ADC is 95 dBFS for a frequency of 97 MHz, and this value is much bigger than the 80 dB required, so, undesired harmonics are not a problem in this case.
The conclusions to be taken are therefore that the ENOB and the typical INL error are the parameters that limit the performance of the ADC. The INL will typically interfere with the 3 bits of lower significance of the codeword. The typical INL error is of 3.5 LSB. The 2 lower significance bits cover up to 3 LSB difference in analog voltage and the 3 lower significant ones bits cover up to 7 LSB jumps in voltage. As far as operation (except noise and distortion) errors are concerned, 13 bits of the ADC are typically 100% reliable.
The ENOB is thus the bottleneck of the ADC performance. Note that none of the ADCs searched were able to achieve or exceed an ENOB of 13 bits. The AD9467 presents a good compromise between speed and accuracy with an ENOB of 12.3 and a sampling rate of 250 MSPS. We now know that of the 16 bits resolution only 12 bits are totally reliable. Even though 30% of the 13th bit isn’t affected by noise or other non correctable typical errors, this advantage will not be taken into account, since it is statistical and hard to measure.
The ADC will inevitably impose, in the simulations performed in Matlab, a minimum signal to noise ratio at the end of the ADC that cannot go any higher than 20 (2 ) ≅72.25 .
Finally to note that the input of the ADC is serial and its ouput is parallel, which means there will be a different output pin for each bit in a given 16 bit codeword.
ADC MSPS Number
of Bits ENOB SFDR Differential
Input Range Analog
Devices AD 9467
250 16 12.3
(140 MHz)
95 dBFS
(140 MHz) 2.5V p-p
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3.2 Digital Filter
3.2.1 Digital Filter Higher Level Design for the FPGA
The band pass filter to be projected has a pass band from 50 MHz to 70 MHz with a maximum attenuation of 3dB and has attenuation bands bellow 45 MHz (inclusive) and above 75MHz (inclusive) with a minimum attenuation of 80 dB.
From here on, the attenuation in the pass band will be designated by and the attenuation in the rejection band will be referred by .
For the required filter’s implementation it is proposed the use of a FPGA of the family Spartan 3A by Xilinx. This family presents DSP slices that work at 250 MHz, each of which contains a multiplier of 18x18 bits, a pre adder of 18 bits and an accumulator of 48 bits. The differential Input/Ouput ports run slightly above 640 Mb/s. Because the DSP slices have parallel buses at their entrance, the minimum I/O rate demanded is 250 Mb/s.
The most complex XC3SD3400A device of Spartan 3A family was picked. It has 126 DSP slices, 373 Kb of distributed RAM and a total block RAM of 2268 Kb. It comprises 309 I/O ports which is quite above the minimum sought of 12. [31], [32]
It will be seen later, the minimum number of DSP slices needed is 73+41=114 with pre adder or 146 + 41 = 187 DSP slices without pre-adder. Since a pre-adder exists, the minimum number of DSP slices necessary in the FPGA is exceeded.
Other FPGA families were considered. The second best option, found for use, is the Virtex 6 device, XC6VLX75T [34]. This family presents DSP slices with much better specifications but which clearly exceed the requirements. For this reason, this last device was not our first option.
It was considered that all the inputs of the FPGA are samples with magnitude between 0 and 1. It is noted that it is possible to normalize any filter entries to a value in this range knowing the maximum absolute value of the samples that arrive to the filter. Thus it was inserted the following data in FDATool (Filter Design Analysis Tool), a tool from the Matlab (Matrix Laboratory) software that allows the simulation of digital filters [35]:
The inputs and outputs of the filter have 18 bits and the coefficients are also represented with 18 bits.
The output of the multiplier is constituted of 36 bits (18 + 18) and lastly the accumulator has a capacity for storing 48 bits.
In the next 3 sub sections, all the possible digital filter high level architectures that can accomplish the digital filter sought will be compared. First, FIR filters will be addressed and then IIR filters will be discussed. Finally, the filter to be implemented will be briefly discussed.