FIR Design in FPGA Conclusions
3.3 Equalizer
The digital equalizer developed has the frequency response depicted in figure 3.5. The shape of this response is a pre-distortion that counteracts the total distortion the signal pass band will suffer in the entire LTE filter.
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Figure 3.5 – Frequency response of the FIR equalizer designed. It is an arbitrary magnitude equalizer of order 40 designed with an Equiripple method. The ripple introduced outside of the signal band (50 to 70 MHz) was checked to be of ∓ 0.3 dB.
The design procedure is briefly explained. The attenuation specifications are given in voltage linear units in the FDATool software in a magnitude vector aligned with a frequency vector. The order of the equalizer is also provided to the software. The order chosen was 40. The higher the order, the better the equalizer matches the specifications, however, the more DSP slices are used and the higher is the latency of the equalizer. This order was a good compromise between not having too high hardware requirements and achieving a good quality of equalizing. The specifications in frequency of the Equiripple equalizer projected, were the ones presented in table 3.5.
Frequency [MHz]
Magnitude Vector/
Voltage Attenuation
Ideal Power Attenuation
[dB]
Actual Power Attenuation [dB]
0 1 0 0.3
45 1 0 0.3
50 1.42 3.05 2.84
55 1.42 3.05 2.84
60 1.09 0.75 1.02
65 1.02 0.17 0.16
68.5 1 0 - 0.12
70 1 0 - 0.16
75 1 0 0.29
125 1 0 - 0.3
Table 3.5 – Equalizer specifications and output response. On the first three columns the data fed to the software along with the intended outcome is shown. On the last column, the actual power attenuation measured in the equalizer graphical response is exhibited.
Other FIR equalizer types were tested like the Least Square and Generalized Equiripple Equalizers.
The least square equalizer achieves less attenuation outside of the signal band (50 to 70 MHz) but the shape and rate of the transitions inside of the signal band, were considered, to slightly lower the quality of the equalizing, in relation to the equalizer chosen.
If the Generalized Equiripple option is used instead the response generated is very similar. The choice between the 2 (Generalized Equiripple and Equiripple) is not very relevant.
An equalizer designed with the method described in this section, cannot have an odd order and therefore will never have an even number of coefficients. For that reason, the equalizer to be used, will be implemented with a systolic parallel FIR architecture, which is the best available option according to what was stated in section 3.2.2.
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3.4 DAC
Since the ADC samples the signal at 250 MSPS, the DAC must also operate at 250 MSPS. The DAC offset error, gain error, DNL and INL errors have the same definition that was given in the appendix, section 3.2, for the ADC. The only difference would now be that, in figures a3.3 to a3.6 in that section, the digital input should be displayed on the x axis and the analog output should be shown on the y axis instead. All the other definitions given in that section, such as the SFDR and the ENOB, still remain valid and unchanged. To note that the SFDR refers to the worst possible spur, so it is a worst case scenario and not a typical one.
Contrary to the ADC used, the DAC has parallel inputs and a serial output. It will have as many inputs as the number of bits in its resolution. The only DACs found that operated at 250 MSPS were the following devices: AD9741, AD9743, AD9745, AD9746 and AD9747.
DAC Resolution
[bits] INL NSD
( 61.44 MHz)
SFDR (70 MHz)
IMD (70 MHz)
AD9741 8 ∓0.05 LSB -162 dB/Hz 70 dBc 80 dBc
AD9743 10 ∓0.10 LSB -174 dB/Hz 70 dBc 80 dBc
AD9745 12 ∓0.25 LSB -185 dB/Hz 70 dBc 80 dBc
AD9746 14 ∓1 LSB -193 dB/Hz 70 dBc 80 dBc
AD9747 16 ∓4 LSB -195 dB/Hz 70 dBc 80 dBc
Table 3.6 – Most important datasheet characteristics of DACs working at 250 MSPS. [37]
NSD is the noise spectral density and IMD refers to the two tone third order intermodulation distortion just like in the mixers case.
There are undesired harmonics that affect the signal. It is certain that these harmonics cause errors in the 14th bit of the DAC (IMD) and they can possibly affect bits 13th and 12th (SFDR).
The output of the DAC has a full scale current between 8.6 mA and 31.7 mA. This current will pass through a 50 ohm resistor and create a voltage between 430 mV (pp) and 1.585 V (pp).
An OFDM signal with 64 orthogonal sub carriers and a tension of 1.585 V (pp) has a power as low as 0.158 mW (simulated, the signal is stochastic, maybe lower values can be obtained) which if spread uniformly by 20MHz gives a power spectral density of −103.576 ≅ −104 . This is possibly a good approximation of the signal present at the output of the ADC. Considering that that is the case, from table 3.6, only the DACs with resolutions equal or above 12 bits, AD9745, AD9746 and AD 9747, would exhibit an SNR bigger than 80 dB (NSD).
We believe the best DAC between all the options is the AD9746. It has an SNR 8 dB better than the AD9745 and only 2 dB worse than the AD9747. Finally, with an INL of 4 LSB, the AD9747 usually has a non linearity error that affects the 3 least significant bits of the input codeword, which means only 13 bits are completely non linearity error free.
As for the AD9746, with an INL of only 1 LSB, 13 bits are also completely non linearity error free.
The DAC to be used is then the AD9746. We will consider as a good approximation, that, of the 14 bit codeword that is the input of the DAC, 12 bits are completely error free (unaffected by noise, distortion or non linearity). This is important for simulation purposes, as will be verified later, in section 5.
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