Introduction Introduction toCMOS VLSIDesign

Introduction to CMOS VLSI

Design

Introduction

Manoel E. de Lima

David Harris - Harvey Mudd College

Introduction

 Integrated circuits: many transistors on one chip.

 Very Large Scale Integration (VLSI): very many

 Complementary Metal Oxide Semiconductor – Fast, cheap, low power transistors

 Today: How to build your own simple CMOS chip – CMOS transistors

– Building logic gates from transistors – Transistor layout and fabrication

 Rest of the course: How to build a good CMOS chip

CMOS VLSI Design

WHY VLSI DESIGN?

Money, technology, civilization

Annual Sales



10

transistors manufactured in 2003



100 million for every human on the planet

0 50 100 150 200

1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002

Year

Global Semiconductor Billings(Billions of US$)

CMOS VLSI Design

Digression: Silicon Semiconductors

 Modern electronic chips are built mostly on silicon substrates

 Silicon is a Group IV semiconducting material

 crystal lattice: covalent bonds hold each atom to four neighbors

Si Si Si

Si Si Si

Si Si Si

http://onlineheavytheory.net/silicon.html

Silicon Lattice

 Transistors are built on a silicon substrate

 Silicon is a Group IV material

 Forms crystal lattice with bonds to four neighbors

Si Si

Si

Si Si

Si

Si Si

Si

CMOS VLSI Design

0: Introduction Slide 7

Dopants

 Silicon is a semiconductor

 Pure silicon has no free carriers and conducts poorly

 Adding dopants increases the conductivity

 Group V: extra electron (n-type)

 Group III: missing electron, called hole (p-type)

As Si Si

Si Si Si

Si Si Si

B Si

Si

Si Si Si

Si Si Si

- +

+ -

p-n Junctions

 A junction between p-type and n-type semiconductor forms a diode.

 Current flows only in one direction

p-type n-type

anode cathode

CMOS VLSI Design

A Brief History

Invention of the Transistor

 Vacuum tubes ruled in first half of 20^th century Large, expensive, power-hungry, unreliable

 1947: first point contact transistor (3 terminal devices)

 Shockley, Bardeen and Brattain at Bell Labs

A Brief History, contd..

 1958: First integrated circuit

 Flip-flop using two transistors

 Built by Jack Kilby (Nobel Laureate) at Texas Instruments

 Robert Noyce (Fairchild) is also considered as a co-inventor

smithsonianchips.si.edu/ augarten/

Kilby’s IC

CMOS VLSI Design

A Brief History, contd.

 First Planer IC built in 1961

 2003

 Intel Pentium 4 processor (55 million transistors)

 512 Mbit DRAM (> 0.5 billion transistors)

 53% compound annual growth rate over 45 years

 No other technology has grown so fast so long

 Driven by miniaturization of transistors

 Smaller is cheaper, faster, lower in power!

 Revolutionary effects on society

 1970’s processes usually had only nMOS transistors

Inexpensive, but consume power while idle

 1980s-present: CMOS processes for low idle power

MOS Integrated Circuits

Intel 1101 256-bit SRAM Intel 4004 4-bit Proc

CMOS VLSI Design

Moore’s Law

 1965: Gordon Moore plotted transistor on each chip

 Fit straight line on semilog scale

 Transistor counts have doubled every 26 months

Year

Transistors

4004

8008 8080 8086

80286 Intel386

Intel486 Pentium

Pentium ProPentium IIPentium III Pentium 4

1,000 10,000 100,000 1,000,000 10,000,000 100,000,000 1,000,000,000

1970 1975 1980 1985 1990 1995 2000

Integration Levels SSI: 10 gates

MSI: 1000 gates LSI: 10,000 gates VLSI: > 10k gates

http://www.intel.com/technology/silicon/mooreslaw/

Transistor Types

 Bipolar transistors

 npn or pnp silicon structure

 Small current into very thin base layer controls large currents between emitter and collector

 Base currents limit integration density

 Metal Oxide Semiconductor Field Effect Transistors

 nMOS and pMOS MOSFETS

 Voltage applied to insulated gate controls current between source and drain

 Low power allows very high integration

 First patent in the ’20s in USA and Germany

 Not widely used until the ’60s or ’70s

CMOS VLSI Design

0: Introduction Slide 15

nMOS Transistor

 Four terminals: gate, source, drain, body

 Gate – oxide – body stack looks like a capacitor – Gate and body are conductors

– SiO₂ (oxide) is a very good insulator

– Called metal – oxide – semiconductor (MOS) capacitor

– Even though gate is

no longer made of metal

n+

p Gate

Source Drain

bulk Si

SiO2 Polysilicon

n+

nMOS Operation

 Body is commonly tied to ground (0 V)

 When the gate is at a low voltage:

– P-type body is at low voltage

– Source-body and drain-body diodes are OFF – No current flows, transistor is OFF

n+

p Gate

Source Drain

bulk Si

SiO2 Polysilicon

n+

D 0 S

CMOS VLSI Design

0: Introduction Slide 17

nMOS Operation Cont.

 When the gate is at a high voltage:

– Positive charge on gate of MOS capacitor – Negative charge attracted to body

– Inverts a channel under gate to n-type

– Now current can flow through n-type silicon from source through channel to drain, transistor is ON

n+

p Gate

Source Drain

bulk Si

SiO2 Polysilicon

n+

D 1 S

pMOS Transistor

 Similar, but doping and voltages reversed – Body tied to high voltage (V_DD)

– Gate low: transistor ON – Gate high: transistor OFF

– Bubble indicates inverted behavior

SiO2

n Gate

Source Drain

bulk Si Polysilicon

p+ p+

CMOS VLSI Design

0: Introduction Slide 19

Power Supply Voltage

 GND = 0 V

 In 1980’s, V_DD = 5V

 V_DD has decreased in modern processes

– High V_DD would damage modern tiny transistors – Lower V_DD saves power

 V_DD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

Transistors as Switches

 We can view MOS transistors as electrically controlled switches

 Voltage at gate controls path from source to drain

g

s d

g = 0

s d

g = 1

s d

g

s d

s d

s d nMOS

pMOS

OFF ON

ON OFF

CMOS VLSI Design

Transistors

Level Symbol Switch Conditions

Strong 1 1 P-switch gate=0, source=V_dd Weak 1 1 N-switch gate=1, source=V_dd Strong 0 0 N-switch gate=1, source=V_ss Weak 0 0 P-switch gate=0, source=V_ss

High impedance Z N-switch gate=0, or P-switch gate=1

0: Introduction Slide 21

Input 0

Output Good 0 Input

1

Output poor 1

Input 0

Output poor 0 Input

1

Output good 1

Input 0

Output Good 0 Input

1

Output poor 1

Input 0

Output poor 0 Input

1

Output good 1

CMOS VLSI Design

0: Introduction Slide 23

CMOS Inverter

A Y

0 1

V

A Y

A Y GND

CMOS Inverter

A Y

0

1 0

V

A=1 Y=0

GND ON OFF

A Y

CMOS VLSI Design

0: Introduction Slide 25

CMOS Inverter

A Y

0 1

1 0

V

A=0 Y=1

GND OFF ON

A Y

CMOS Inverter

VinVin VoutVout VddVdd

VssVss

CCloadload

Q1Q1 Q2Q2

IIdd

1- 1- Vin = VddVin = Vdd

Análise do circuito:

Análise do circuito:

Vdd=+5V Vdd=+5V

0V0V

VoutVout Roff

Roff

RonRon

Cálculo de Vout

Vdd = Ids(Roff+Ron) =>

Vdd = Ids.Roff+Ids.Ron =>

Vdd = Ids.Roff+Vout =>

Vout = Vdd-Ids.Roff 0V^ IdsIds

Ron < 1 Kohms Roff 10¹⁰Kohms

Ids é pequeno, mas Roff é bastante grande



CMOS VLSI Design

CMOS Inverter

• Note que V_h = 5V, V_L = 0V, e que I_ds = 0A.

• Isto significa que não existe praticamente dissipação de potência.

CMOS Inverter

+5V

GNDGND

V_ih=´1´

R +5V

GNDGND I_ol I_il Out

In

V_ol(max) V_il(max)

Tempo (seg) Tensão(V)

V_il(max) Nível ´0´

Capacitor carregado (´1´)

Transistor conduz

R_on  1 K

Transistor não conduz

R_on  1 K

CMOS VLSI Design

CMOS Inverter

VinVin VoutVout VddVdd

VssVss

CCloadload

Q1Q1 Q2Q2

IIdd

2- 2- Vin = 0VVin = 0V

Análise do circuito:

Análise do circuito:

Vdd=+5V Vdd=+5V

0V0V

VoutVout Ron Ron

RoffRoff

Cálculo de Vout

Vdd = Ids(Roff+Ron) =>

Vdd = Ids.Roff+Ids.Ron =>

Vdd = Vout+Ids.Ron =>

Vout = Vdd-Ids.Ron Vdd=5V^ IdsIds

Ron < 1 Kohms Roff 10¹⁰Kohms Ids é muito pequeno



CMOS Inverter

• Note que V_h = 5V, V_L = 0V, e que I_ds = 0A.

• Isto significa que não existe praticamente dissipação de potência.

CMOS VLSI Design

CMOS Inverter

+5V

GNDGND

V_il=0

R +5V

GNDGND I_oh I_ih Out

In

V_oh(min) V_ih(min)

Tempo (seg) Tensão(V)

V_ih(min) Nível ´1´

Capacitor

X

Transistor não conduz

R_off  10¹⁰

Transistor conduz

R_on  1 K

CMOS NAND Gate

A B Y

0 0

0 1

1 0

1 1

A B

Y

CMOS VLSI Design

0: Introduction Slide 33

CMOS NAND Gate

A B Y

0 0 1

0 1

1 0

1 1

A=0 B=0

Y=1 OFF

ON ON

OFF

CMOS NAND Gate

A B Y

0 0 1

0 1 1

1 0

1 1

A=0 B=1

Y=1 OFF

OFF ON

ON

CMOS VLSI Design

0: Introduction Slide 35

CMOS NAND Gate

A B Y

0 0 1

0 1 1

1 0 1

1 1

A=1 B=0

Y=1 ON

ON OFF

OFF

CMOS NAND Gate

A B Y

0 0 1

0 1 1

1 0 1

1 1 0

A=1 B=1

Y=0 ON

OFF OFF

ON

CMOS VLSI Design

Lógica Combinacional

 Porta NAND ^{saídasaída A}₀ ^A_{0 11}

00 11 11 BB

11 1 01 0

AA BB

P P

N

N

Vcc (‘1’)

GND (‘0’)

saída

Vcc

GND A

B

Saída Saída

GND A

B C

n

A B C ⁿ

Vcc

Porta NAND de n-entradas (A+B)

(A B)

Dual Lógico Dual Lógico

CMOS NOR Gate

A B Y

0 0 1

0 1 0

1 0 0

1 1 0

A B

Y

CMOS VLSI Design

Lógica Combinacional

 Porta NOR

AA ^{N N} BB

P

Vcc (‘1’)

GND (‘0’)

saída

P

Vcc

GND A

B

saída

Saída Vcc

n

A B C

A B C ⁿ

GND

saída

saída A A

00 11

00 11 00 BB

11 0 00 0

(A B)

(A+B)

Dual Lógico Dual Lógico

3-input NAND Gate

 Y pulls low if ALL inputs are 1

 Y pulls high if ANY input is 0

A B

Y

C

CMOS VLSI Design

0: Introduction Slide 41

Summary

 MOS Transistors are stack of gate, oxide, silicon

 Can be viewed as electrically controlled switches

 Build logic gates out of switches