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31 aula

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Interface Hardware-Software

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IHS - §3 ISA Data Transfer 2

Tópicos

1) Assembler Directives 2) Moving data

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Tópicos

1) Assembler Directives 2) Moving data

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IHS - §3 ISA Data Transfer 4

Assembly Language

Three different classes of statements Instructions

Assembler directives (pseudo-ops) Macros

Directives are nonexecutable and do not generate any machine language instructions

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The

BITS directive

Syntax: BITS XX (where XX=16 or 32)

Generate code designed to run on a processor operating in 16-bit or 32-bit mode

Used rarely explicitly: The output format employed during assembling specifies the mode

The elf, macho or win32 format defaults to 32-bit mode The bin output format defaults to 16-bit mode

A special bit (operand size attribute / address size attribute) in the segment descriptors (the “invisible” part of the CS and DS/SS) indicates the operation mode

Is it possible to override the default, i.e., can we use 32-bit operands/addresses in the 16-bit mode (and vice versa)?

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IHS - §3 ISA Data Transfer 6

Storage Allocation for Initialized Data

Five basic forms (define directive): DB value (allocates one byte)

DW value (allocates two bytes = word)

DD value (allocates four bytes = doubleword) DQ value (allocates eight bytes = quadword) DT value (allocates ten bytes)

Two's complement representation is used to store negative values The assembler assigns contiguous memory space for the variables

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Example

Question: What does the following code snippet do?

Analysis:

Real mode

DB 66H supplies the single-byte operand size prefix, changing the default of the following MOV instruction (AX ➡ EAX)

DW 058bH adds 16-bit to the instruction code Thus, the corresponding 32-bit code would read:

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IHS - §3 ISA Data Transfer 8

Storage Allocation for Uninitialized Data

Five basic forms (reserve directive): RESB (reserves one byte)

RESW (reserves two bytes) RESD (reserves four bytes) RESQ (reserves eight bytes) REST (reserves ten bytes)

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The

EQU Directive

Syntax: name EQU expression Directives to define constants

Increases program readability Example:

NUM_OF_STUDENTS EQU 90 mov ECX, NUM_OF_STUDENTS is equal to

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IHS - §3 ISA Data Transfer 10

Tópicos

1) Assembler Directives 2) Moving data

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Data Transfer Instructions

You can transfer data between:

Register ← Register Register ← Memory Register ← Immediate Register ← Port Memory ← Register Memory ← Memory Memory ← Immediate Port ← Register

May differ in the amount of amounts transferred: One value

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IHS - §3 ISA Data Transfer 12

The

MOV Instruction

Move; Syntax: mov dest, src

Transfers the value from source to destination, where the following combinations are possible:

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More About the

MOV Instruction

Instruction is coded differently depending on its operands: Example: mov ax, 0x30 and mov al, 0x30

Assembler examines register size and encodes the immediate according to this size

Recall that for operations involving memory, the address specified is the least significant byte (Little Endian)

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IHS - §3 ISA Data Transfer 14

How to Know the Size of an Operand?

In cases where one operand is an immediate and the other is a memory position, qualifiers must be placed before the memory position:

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The

MOVSX and MOVZX Instructions

Move with Sign-Extension; Syntax:

movsx reg16, src8 (ou reg32, src8 ou reg32, src16) Move with Zero-Extend; Syntax:

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IHS - §3 ISA Data Transfer 16

MOVSX and MOVZX Operation

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What is a stack?

A last-in-first-out (LIFO) data structure

Only words (i.e.,16-bit data) or double words (i.e.,32-bit data) are saved on the stack, never a single byte.

The stack grows toward lower memory addresses

The SS register is used for the segment base address

The offset value comes from either the SP register (for 16-bit addresses) or the ESP register (for 32-bit addresses).

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IHS - §3 ISA Data Transfer 18

The

PUSH Instruction

Syntax: push src

Decrements the stack pointer and then stores the source operand on the top of the stack

push ESP pushes the ESP register value before it was

decremented by the push instruction; push SP pushes the decremented SP value onto the stack

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PUSH Operation

Top of stack: SS:SP or SS:ESP The address-size attribute of the stack segment determines the stack pointer size (SP or ESP) The operand-size attribute of the current code segment determines the amount the stack pointer is decremented (2 bytes or 4 bytes).

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IHS - §3 ISA Data Transfer 20

The

PUSHA and PUSHAD Instructions

Pushes all eight 16-bit (Syntax: pusha) or 32-bit (Syntax: pushad) general registers onto the stack.

Ordem:

SP é decrementado em 8 * quantidade de bytes de cada registrador

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The

PUSHF and PUSHFD Instructions

Pushes the 16-bit (Syntax: pushf) or 32-bit (Syntax: pushfd) flags register (i.e. FLAGS or EFLAGS) onto the stack

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IHS - §3 ISA Data Transfer 22

The

POP Instruction

Syntax: pop dest

Loads the value from the top of the stack to the location specified with the destination operand and then increments the stack pointer. POP ESP increments the stack pointer (ESP) before data at the old top of stack is written into the destination.

dest can be:

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POP Operation

Top of stack: SS:SP or SS:ESP The address-size attribute of the stack segment determines the stack pointer size (SP or ESP) The operand-size attribute of the current code segment determines the amount the stack pointer is incremented (2 bytes or 4 bytes).

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IHS - §3 ISA Data Transfer 24

The

POPA and POPAD Instrcutions

Pops all eight 16-bit (Syntax: popa) or 32-bit (Syntax: popad) general registers from the top of the stack

Ordem:

The value that would be stored in SP / ESP is discarded so as not to change the value of SP / ESP in the middle of the operation.

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IHS - §3 ISA Data Transfer 26

The

POPF and POPFD Instructions

Pops the 16-bit (Syntax: popf) or 32-bit (Syntax: popfd) flags register (FLAGS or EFLAGS) from the top of the stack.

Bits 16 (VM flag) and 17 (RF flag) of the EFLAGS register are not affected by this instruction

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The

LEA Instruction

Load effective address; Syntax: lea dest, src

Computes the effective address of a memory operand given by src and stores it in the dest register

The dest must be either a 16- or 32-bit register (but not a segment register)

dest=16-bit but src=32-bit: Only the lower 16-bits are stored

dest=32-bit but src=16-bit: The effective address is zero-extended to 32 bits

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IHS - §3 ISA Data Transfer 28

Example

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IHS - §3 ISA Data Transfer 30

The

IN and OUT Instructions

Input from port; Syntax: in dest, port

dest must be the AL, AX, or EAX register

port is an 8-bit immediate value (addresses 0x0 to 0xFF) or port is in DX allowing to access the complete I/O space (0x0 to 0xFFFF)

Output to port; Syntax: out port, src

src must be in the AL, AX, or EAX register.

port is an 8-bit immediate value (0x00 to 0xFF) or port is in DX (any port between 0x00 and 0xFFFF)

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IHS - §3 ISA Data Transfer 32

The

XCHG Instruction

Syntax: xchg dest, src

Exchanges the values of the two operands src and dest

The operands can be two general-purpose registers or a register and a memory location

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The

BSWAP Instruction

Byte Swap; Syntax: bswap src

Reverses the byte order of a 32-bit register src (Byte swap)

This effectively converts a value from little endian to big endian, and vice versa

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IHS - §3 ISA Data Transfer 34

The

LDS/LES/LFS/LGS/LSS Instructions

Load far pointer; Syntax: lds dest, src

Loads a far pointer (segment selector and offset) from src into dest (offset = first two or four bytes) and DS (selector = next two bytes) Depending on the operand-size attribute, the offset is 32-bits or 16-bits. Thus src specifies a 48-bit or 32-bit pointer in memory.

The instructions les, lfs, lgs, lss load the selector into the ES, FS, GS or SS segment registers, respectively

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Referências

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