An Ultra Low Power Amplifier-less Sigma-Delta Modulator for Audio Applications

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Dimo Atanasov Naydenov

Licenciado em

Ciências de Engenharia Eletrotécnica e de Computadores

An Ultra Low Power Amplifier-less Σ∆ Modulator

for Audio Applications

Dissertação para obtenção do Grau de Mestre em Engenharia Eletrotécnica e de Computadores

Orientador: Doutor Nuno Filipe Silva Veríssimo Paulino, Prof. Auxiliar, Universidade Nova de Lisboa

Júri

Presidente: Doutor Rodolfo Alexandre Duarte Oliveira - FCT/UNL Vogais: Doutor Nuno Filipe Silva Veríssimo Paulino - FCT/UNL

Doutor João Pedro Abreu de Oliveira - FCT/UNL

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An Ultra Low Power Amplifier-less Σ∆ Modulator for Audio Applications

The Faculdade de Ciências e Tecnologia and the Universidade NOVA de Lisboa have the right, perpetual and without geographical boundaries, to file and publish this dissertation through printed copies reproduced on paper or on digital form, or by any other means known or that may be invented, and to disseminate through scientific repositories and admit its copying and distribution for non-commercial, educational or research purposes, as long as credit is given to the author and editor.

Este documento foi gerado utilizando o processador (pdf)LA_{TEX, com base no template “novathesis” [1] desenvolvido no Dep. Informática da FCT-NOVA [2].} [1] https://github.com/joaomlourenco/novathesis [2] http://www.di.fct.unl.pt

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If no one comes from the future to stop you from doing it, then how bad of a decision can it really be?

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Ac k n o w l e d g e m e n t s

I would like to thank dearly to my advisor Prof. Nuno Paulino for the opportunity to do research in state of the art technology in the area of electronics and the shown support, availability, dedication, commitment and patience.

An acknowledgement to the Department of Electrical Engineering of Faculdade de Ciências e Tecnologia of Universidade NOVA de Lisboa for nurturing education and culture for all the academic community though the shared teachings. To Prof. João Oliveira, a special thank you for the trust he put on me to work by his side and the provided opportunities. To Prof. João Goes and Prof. Rui Tavares for leading me to persue electronics by their own and unique ways.

I would like to give the most heartfelt thanks to my family for giving me the oppor-tunities and support through my life that made me what I am today. To Inês Caupers for being by my side through the difficult times, new adventures and hard decisions.

A warm and special appreciation to my friends and people who have been by my side and have helped me in one way or another during this and other journeys. Specifi-cally to André Vaz, António Mendes, Bruno Campos, Bruno Patrício, Davidson Andrade, Diogo Alves, Duarte Gonçalves, Frederico Chaves, Hussein Rassid, Nuno Pereira, Ricardo Madeira and Susana Valente.

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A b s t r a c t

In the current digital age, electronic devices are becoming increasingly more critical, especially mobile devices and "always-listening" devices such as virtual personal assis-tants. To gather data from the real world, which in this case is voice audio, digital devices need to convert the analog input signals captured by a microphone to a digital stream. The process of data conversion is usually an energy expensive process, where lower power drawing implementations would benefit battery powered devices and provide less energy consuming "always-listening" devices.

One of the most appealing Analog to Digital Converter (ADC) implementations are done using Sigma-Delta Modulators (Σ∆Ms) due to their use of oversampling that allows the noise to be transferred to higher frequencies that can be posteriorly eliminated by a decimation filter. In discrete timeΣ∆Ms, implemented with Switched-Capacitor (SC), the full capacitor charging consumes a considerable amount of power; to improve this aspect, a partial capacitor charge could be implemented, allowing less energy to be used in each clock cycle.

In this thesis, a Multi-stAge Noise SHaping (MASH) 2+1Σ∆M is implemented with Metal-Insulator-Metal (MIM) capacitors and Unsilicided P+ Polysilicon resistors with a sampling frequency of 10 MHz and a bandwidth of 20 kHz, to evaluate the practical feasibility of the architecture. Due to the expected decrease in performance when com-pared to the original circuit, theΣ∆M is improved and stabilized through the temperature range. The finalized MASH 2+1Σ∆M achieves 86.755 dB of Signal-to-Noise-and-Distor-tion Ratio (SNDR) with 2 kHz, 300 mV input signal while using an active silicon area of 96439.127 µm2or around 0.0964 mm2 (this active area does not contain the Digital Cancellation Logic (DCL) circuitry).

Keywords: Analog to Digital Converter (ADC), Multi-stAge Noise SHaping (MASH), Sigma-Delta Modulator (Σ∆M), Ultra Incomplete Settling (UIS), Switched-Capacitor (SC), Passive Integrator, Discrete Time (DT)

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R e s u m o

Na actual era digital, dispositivos electrónicos são cada vez mais críticos para as nossas vidas, especialmente dispositivos móveis and dispositivos que estão "sempre à escuta" tais como assistentes virtuais inteligentes. Para obter dados do mundo real, que neste caso é áudio de voz, os dispositivos digitais necessitam de converter os sinais analógicos provenientes de um microfone para uma saída digital. O processo de conversão de dados é usualmente um processo energeticamente dispendioso, onde implementações que gastem menos energia beneficiam dispositivos cuja fonte energética é uma bateria e originam dispositivos "sempre à escuta" que consomem menos energia.

Uma das implementações mais apelativas dos Conversores Analógico para Digital (CAD) é com moduladoresΣ∆ (MΣ∆) devido ao seu uso de oversampling que permite a deslocação do ruído para frequências mais altas, que pode ser posteriormente eliminado por um filtro de dizimação. MΣ∆ em tempo discreto, implementado com Condensadores-Comutados (CC), o carregamento completo dos condensadores durante o ciclo consome uma quantidade de energia considerável; para melhorar este aspecto, pode ser implemen-tada a carga parcial do condensador, permitindo assim um menor uso de energia por ciclo de relógio.

Nesta tese, um MASH 2+1 MΣ∆ é implementado com condensadores de Metal-Isolador-Metal e resistências de P+ Polisilício Não-Siliciado com frequência de amostragem de 10 MHz e uma largura de banda de 20 kHz. Devido à perda de desempenho esperada quando comparado com o circuito original, o MΣ∆ é melhorado e estabilizado ao longo da variação de temperatura. O MASH 2+1 MΣ∆ finalizado atinge 86.755 dB de SNDR com um sinal de entrada de 2 kHz e 300 mV, enquanto utiliza 96439.127 µm2ou 0.0964 mm2 de área activa de silício (esta área não inclui o circuito de Lógica de Cancelamento Digital (LCD)).

Palavras-chave: Conversor Analógico para Digital (CAD), Multi-stAge Noise SHaping (MASH), Modulator Sigma-Delta (MΣ∆), Regime Transitório Ultra Incompleto (RTUI), Condensadores-Comutado (CC), Integrator Passivo, Tempo Digital (TD)

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C o n t e n t s

List of Figures xv

List of Tables xxi

Acronyms xxiii

1 Introduction 1

1.1 Background and Motivation . . . 1

1.2 Contributions . . . 2

1.3 Thesis Organization . . . 3

2 Σ∆ Modulation and Data Conversion Fundamentals 5 2.1 Σ∆ Modulation . . . 5

2.2 Signal Conversion Fundamentals . . . 6

2.2.1 Analog-to-Digital Converter Structure . . . 8

2.2.2 Quantization . . . 9

2.2.3 Oversampling . . . 10

2.2.4 Performance Metrics . . . 10

2.3 Σ∆ Modulation Basics . . . 13

2.4 Low Power Σ∆ Modulators . . . 19

2.4.1 Low Power Techniques . . . 19

2.4.2 Passive Σ∆M . . . 20

2.4.3 Feedback and Feedforward . . . 22

2.4.4 Multi-bit vs. Single-bit Quantization . . . 23

2.4.5 Comparison of SimilarΣ∆M . . . 24

3 Architecture’s High Level Model 27 3.1 Passive SC Integrator Implementation . . . 27

3.1.1 Transfer Function . . . 28

3.1.2 Thermal Noise Analysis . . . 29

3.2 Σ∆ Modulator Architecture . . . 30

3.2.1 1st_{Order Modulator . . . .} ₃₀

3.2.2 2nd_{Order Modulator . . . .} ₃₂

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3.2.3 Proposed Architecture . . . 33

3.3 High Level Model . . . 34

3.4 Component Value Fine Tuning . . . 37

4 Electrical Circuits, Layout and Simulation 45 4.1 Electrical Circuits . . . 45

4.1.1 Digital Circuits . . . 45

4.1.2 Analog Circuits . . . 54

4.1.3 Switching Circuits . . . 61

4.1.4 Feedback Control and Reference Voltages . . . 69

4.2 3rd Order MASH 2+1 Σ∆M Circuit Schematic and Simulation Results . 71 4.2.1 Circuit Schematic . . . 71

4.2.2 MASH 2+1 Σ∆M Baseline Performance . . . 72

4.2.3 2nd_{Order Σ∆M with Real Resistors and Capacitors . . . .} ₇₂

4.2.4 2nd_{Order Σ∆M with Improved Capacitor Values . . . .} ₈₁

4.2.5 2ndOrder Σ∆M with Phase Buffers . . . 84

4.2.6 MASH 2+1 Σ∆M with Adjusted DCL parameters . . . 84

4.2.7 Summary . . . 86

4.3 Circuit Layout Design . . . 87

4.3.1 Two Phase Generator . . . 87

4.3.2 Monostable Circuit . . . 88 4.3.3 Phase Generation . . . 91 4.3.4 Bit-Phase Generator . . . 91 4.3.5 Flip-Flop . . . 95 4.3.6 Comparator . . . 96 4.3.7 Buffer . . . 97 4.3.8 Switches . . . 99

4.3.9 Amplifiers G₂and G_mid . . . 104

4.4 3rd _{Order MASH 2+1 Σ∆M Circuit Layout and Simulation Results . . .} ₁₀₄

4.4.1 Simulation results . . . 106

5 Conclusions and Future Work 109 5.1 Conclusions . . . 109

5.2 Future Work . . . 110

Bibliography 113

A Circuit and Layout Design on ST Microelectronics 65 nm CMOS Technology 119

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L i s t o f F i g u r e s

2.1 Sampling and quantization process. . . 6

2.2 Time domain sampling process. . . 7

2.3 Frequency domain sampling process. . . 8

2.4 Over and under sampling in frequency domain. . . 8

2.5 Generic block diagram for an ADC. . . 8

2.6 Ideal quantizer characteristics. . . 9

2.7 Spectral density of quantization noise. . . 10

2.8 Performance metrics. . . 12

2.9 Block diagram for aΣ∆M ADC. . . 13

2.10 Block diagram for a first orderΣ∆ modulator. . . 13

2.11 Frequency response of ST F and N T F for a first orderΣ∆M. . . 15

2.12 Block diagram for a second orderΣ∆ modulator. . . 16

2.13 Frequency response of ST F and N T F for a second orderΣ∆M. . . 17

2.14 Block diagram for a MASH 1+1Σ∆M. . . 18

2.15 CT passive RC integrator. . . 20

2.16 DT SC passive integrator. . . 21

2.17 Capacitor voltage in response for a step input. . . 21

2.18 Schematic of a SC passive integrator in UIS region. . . 22

2.19 Generic block diagram with arbitrary feedforward and feedback paths for a second orderΣ∆M. . . 22

2.20 Quantization staircase characteristics. . . 23

3.1 DT SC passive integrator under UIS conditions. . . 27

3.2 Capacitor’s voltage along each phase. . . 28

3.3 Linear block diagram model for a first order DTΣ∆M working under UIS conditions. . . 31

3.4 STF and NTF plot. . . 32

3.5 Linear block diagram model for a second order DTΣ∆M working under UIS conditions. . . 32

3.6 Linear block diagram model for the proposed MASH 2+1 architecture. . . 34

3.7 Circuit schematic of second orderΣ∆M. . . 35

3.8 Circuit schematic for the 1st orderΣ∆M. . . 36 xv

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3.9 Dynamic range as function of R1. . . 41

3.12 Dynamic range as function of C1. . . 42

3.15 Dynamic range as function of Gf b1. . . 44

3.16 Dynamic range as function of Gf b2. . . 44

4.1 CMOS NOT gate. . . . 46

4.2 Simulated CMOS NOT gate transfer function. . . . 46

4.3 CMOS NAND gate. . . . 47

4.4 CMOS AND gate. . . . 47

4.5 CMOS NOR gate. . . . 48

4.6 Traditional CMOS NOR gate. . . . 48

4.7 CMOS inverter based buffer. . . 49

4.8 CMOS inverter based 100 ps delay. . . 50

4.9 Simulated voltages for the 100 ps delay circuit. . . 50

4.10 Pulse generator. . . 50

4.11 Simulated pulse generator output. . . 51

4.12 Rising edge triggered monostable circuit schematic. . . 51

4.13 Simulated voltages for the rising edge triggered monostable circuit. . . 52

4.14 Phase generator schematic. . . 53

4.15 Simulated phase generator outputs. . . 53

4.16 Simulated output phases generated by the phase generator with monostable circuit. . . 53

4.17 D-type flip-slop schematic. . . 54

4.18 Simulated output for the gated D latch. . . 54

4.19 Circuit schematic of amplifier G₂with bias compensation. . . 56

4.20 G_midbias and common voltage as a function of temperature. . . 57

4.21 Bode diagram for compensation amplifier for amplifier G₂at typical device speed and 27◦_{C. . . .} ₅₉

4.22 Bode diagram for amplifier G₂at typical device speed at 27◦_{C. . . .} ₅₉

4.23 Circuit schematic amplifier G_midwith bias compensation. . . 62

4.24 G_midbias and common voltage as a function of temperature. . . 64

4.25 Bode diagram for compensation amplifier for amplifier G_midat typical device speed and 27◦_{C. . . .} ₆₄

4.26 Bode diagram for amplifier G_midat typical device speed at 27◦_{C. . . .} ₆₅

4.27 Circuit of the comparator. . . 65

4.28 Comparator input and output signals. . . 67

4.29 MOS switches. . . 67 xvi

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L i s t o f F i g u r e s

4.30 Closed state resistance for MOS transistors as a function of the capacitor plate

voltage. . . 68

4.31 Transmission gate switch circuit. . . 68

4.32 Closed state transmission gate characteristics. . . 69

4.33 Clock bootstrapped NMOS switch circuit. . . . 70

4.34 Circuit schematic of a passive integrator with feedback paths and reference voltages. . . 71

4.35 Complete circuit schematic of the first stageΣ∆M. . . 73

4.36 Complete circuit schematic of second stageΣ∆M. . . 74

4.37 Complete logic schematic for monostable phase generation. . . 75

4.38 Complete logic schematic for phase generation for Vref, D-Flip-Flop and Com-parator control. . . 75

4.39 FFT with 20 k points with Blackman-Harris window of the output bit-stream for a 300 mV, 2 kHz input signal, considering thermal noise. . . 76

4.40 Equivalent model. . . 76

4.41 FFT with 20 k points with Blackman-Harris window of the output bit-stream of the second orderΣ∆M for a 300 mV, 2 kHz input signal, considering ther-mal noise. . . 77

4.42 Circuit schematic of a passive integrator with feedback paths, reference volt-ages and parasitics. . . 77

4.43 Simplified passive integrator circuit. . . 78

4.44 Closed switches equivalent circuit. . . 78

4.45 Voltage v_C₁plot with different variable values. . . 80

4.46 Switch sizing circuit. . . 80

4.47 Closed state resistance for MOS transistors. . . 81

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4.53 FFT with 20 k points with Blackman-Harris window of the output bit-stream for a 300 mV, 2 kHz input signal, considering thermal noise. . . 85 4.54 DCL parameter improvement. . . 85 4.55 FFT with 20 k points with Blackman-Harris window of the output bit-stream

for a 300 mV, 2 kHz input signal, considering thermal noise. . . 86 4.56 Two phase generator circuit layout design. . . 88 4.57 Phase generator output signals from schematic and circuit layout extraction

level transient simulation at 27◦_{C and TT transistor speed. . . .} ₈₈

4.58 Monostable circuit layout design. . . 90 4.59 Rising edge triggered monostable circuit signals from schematic and circuit

layout extraction level transient simulation at 27◦_{C and TT transistor speed.} ₉₀

4.60 Monostable circuit output rise and fall edge from schematic and circuit layout extraction level transient simulation at 27◦_{C and TT transistor speed. . . .} ₉₁

4.61 Phase generation circuit. . . 91 4.62 Phase generation circuit layout design. . . 92 4.63 Phase generation circuit output from circuit layout extraction level transient

simulation at 27◦_{C and TT transistor speed. . . .} ₉₂

4.64 Phase generator output rise and fall edges from circuit layout extraction level transient simulations at 27◦_{C and TT transistor speed. . . .} ₉₂

4.65 Bit-phase generator circuit layout design. . . 93 4.66 Bit-phase signals from schematic and circuit layout extraction level transient

simulations at 27◦_{C and TT transistor speed. . . .} ₉₄

4.67 Bit-phase output signal edges from schematic and circuit layout extraction level transient simulations at 27◦_{C and TT transistor speed. . . .} ₉₄

4.68 D-Flip-Flop circuit layout design. . . 95 4.69 DFF signals from schematic and circuit layout extraction level transient

simu-lations at 27◦_{C and TT transistor speed. . . .} ₉₅

4.70 DFF output signal from schematic and circuit layout extraction level transient simulations at the defined corners. . . 96 4.71 Comparator circuit layout design. . . 97 4.72 Buffer’s circuit layout design. . . 98 4.73 Buffer output signal from schematic and circuit layout extraction level

tran-sient simulation at 27◦_{C and TT transistor speed. . . .} ₉₈

4.74 Buffer output signal rise and fall edge from schematic and circuit layout ex-traction level transient simulations at 27◦_{C and TT transistor speed. . . . .} ₉₉

4.75 MOS device switch circuit layout design. . . 99 4.76 Circuit layout extraction closed state resistance for MOS transistors from DC

level simulation at 27◦_{C and TT transistor speed. . . .} ₁₀₀

4.77 Circuit layout extraction closed state resistance for MOS transistors from DC level simulation at the defined corners. . . 100 4.78 Transmission gate layout design. . . 101

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L i s t o f F i g u r e s

4.79 Transmission gate switch closed state resistance from schematic and circuit layout extraction level DC simulations at 27◦_{C and TT transistor speed. . .} ₁₀₁

4.80 Transmission gate switch closed state resistance from circuit layout extraction DC simulations at the defined corners. . . 102 4.81 Clock bootstrapped switch circuit layout design. . . 102 4.82 Clock bootstrapped switch signals from circuit layout extraction level

tran-sient simulation at 27◦_{C and TT transistor speed. . . .} ₁₀₃

4.83 Schematic and circuit layout extraction level transient simulation of the clock bootstrapped switch boosted voltage rise and fall edge at 27◦_{C and TT}

tran-sistor speed. . . 103 4.84 Amplifiers G₂and G_midcircuit layout. . . 105 4.85 MASH 2+1Σ∆M complete circuit layout design. . . 107 4.86 MASH 2+1Σ∆M without DCL schematic level power consumption

distribu-tion during transient simuladistribu-tion. . . 108

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L i s t o f Ta b l e s

2.1 Comparison between state of the art low powerΣ∆M ADCs. . . 25

3.1 Proposed parameter sizes to achieve improved performance. . . 40

4.1 Transistor dimensions for NOT gate. . . . 46

4.2 Transistor dimensions for NAND gate. . . . 47

4.3 Transistor sizes for buffer. . . 49

4.4 Transistor dimensions for 100 ps delay. . . 50

4.5 Monostable circuit lumped element values. . . 52

4.6 Transistor dimensions for the bias compensation circuit of amplifier G2. . . 58

4.7 Transistor dimensions for amplifier G2. . . 58

4.8 Temperature and device speed corners for amplifier G₂compensation. . . . 60

4.9 Temperature and device speed corners for amplifier G₂. . . 60

4.10 Transistor dimensions for the bias compensation circuit of amplifier G_mid. 63 4.11 Transistor dimensions for amplifier G_mid. . . 63

4.12 Temperature and device speed corners for amplifier G_midcompensation. . 66

4.13 Temperature and device speed corners for amplifier G_mid. . . 66

4.14 Transistor dimensions for the comparator. . . 67

4.15 Transistor dimensions for the MOS switch. . . 68

4.16 Transistor dimensions for the transmission gate. . . 69

4.17 Transistor dimensions for the clock bootstrapped switch. . . 70

4.18 New transistor sizes for a MOS switch. . . 80

4.19 Capacitor sizes to achieve improved performance. . . 83

4.20 Summarised DCL parameters. . . 85

4.21 Summarised performance evolution of the second orderΣ∆M for a 2 kHz input signal with 300 mV of amplitude and transient noise. . . 86

4.22 Simulation corners. . . 87

4.23 Two phase generation phase interval obtained through transient simulation of the circuit layout extraction level at the defined corners. . . 89

4.24 Monostable circuit resistive and capacitive element values. . . 89

4.25 Monostable circuit pulse width obtained through circuit layout extraction level transient simulation at the defined corners. . . 89

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4.26 Phase generation circuit signal rise and fall time obtained through circuit layout extraction level transient simulation at the defined corners. . . 93 4.27 Bit-phase output signal rise and fall time obtained through circuit layout

ex-traction level transient simulations at the defined corners. . . 93 4.28 Buffer generated delay obtained through transient simulation of the circuit

layout extraction level at the defined corners. . . 98 4.29 Transmission gate maximum resistance obtained through circuit layout

ex-traction level DC simulations at the defined corners. . . 101 4.30 Clock bootstrapped switch boosted voltage from transient simulation at the

defined corners. . . 104 4.31 Amplifier G₂performance from schematic and circuit layout extraction. . . 104 4.32 Amplifier G_midperformance from schematic and circuit layout extraction. 106 5.1 Summarised performance of the MASH 2+1Σ∆M. . . 110 5.2 Summarised performance evolution of the second order Σ∆M for a 2 kHz

input signal with 300 mV of amplitude and transient noise. . . 110

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Ac r o n y m s

Σ∆M Sigma-Delta Modulator. AAF Anti-Aliasing Filter.

ADC Analog to Digital Converter.

CMOS Complementary Metal-Oxide-Semiconductor. CMRR Common-Mode Rejection Ratio.

CT Continuous Time.

DAC Digital to Analog Converter. DC Direct Current.

DCL Digital Cancellation Logic. DEM Dynamic Element Matching. DFF D-Flip-Flop.

DNL Differential Non-linearity.

DR Dynamic Range.

DT Discrete Time.

EDA Electronic Design Automation. ENOB Effective Number of Bits. FFT Fast Fourier Transform. FoM Figure of Merit.

IC Integrated Circuit. INL Integral Non-linearity. IoT Internet of Things. KCL Kirchhoff’s Current Law.

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KVL Kirchhoff’s Voltage Law. LSB Least Significant Bit.

MASH Multi-stAge Noise SHaping. MIM Metal-Insulator-Metal.

NMOS N-type Metal-Oxide-Semiconductor. NTF Noise Transfer Function.

OSR Oversampling Ratio.

PMOS P-type Metal-Oxide-Semiconductor. PSD Power Spectral Density.

PSRR Power Supply Rejection Ratio. S/H Sample and Hold.

SC Switched-Capacitor.

SNDR Signal-to-Noise-and-Distortion Ratio. SNR Signal-to-Noise Ratio.

STF Signal Transfer Function. THD Total Harmonic Distortion. UIS Ultra Incomplete Settling.

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I n t r o d u c t i o n

1.1 Background and Motivation

In the computer age, every electronic device has the need to interact with the physi-cal world. Digital circuitry provides computational and signal processing power, but it can not interact directly with the physical world. So, data converters arose due to this incompatible nature of the inherently analog physical world – which contains continuous signals that can take an infinite amount of values at any moment – and the digital core – where a signal is represented as a time-independent and finite amount of values by bits of information. Those devices come as Analog to Digital Converter (ADC) and Digital to Analog Converter (DAC) that need constant improvement in speed and accuracy due to the advancements in speed and density of integrated circuits.

In a time with an ever-growing number of Internet of Things (IoT) devices and global energy sustainability mind-set, energy consumption must be minimal, especially in battery-powered devices. Advances in fabrication processes have led to diminished tran-sistor feature size, forcing lower supply voltages and consequentially obtaining lower power consumption; this is true for digital circuits, but their analog counter-parts size and power relation does not go quite the same way.

Current generation of portable audio applications require higher resolution, high lin-earity, low distortion and high dynamic range along side with low power and circuit area. Data converters can be classified as Nyquist rate or oversampling converters, according to their Oversampling Ratio (OSR). Nyquist rate converters sample the input signal at a frequency that is two times the signal bandwidth and there is a one-to-one correspon-dence between the input and output signals – each sample is processed independently – and this type of converter lacks memory. The matching between analog components determines the linearity and accuracy of this type of converters, which makes it difficult

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to achieve high resolutions [3]. On the other hand, oversampling converters in most Com-plementary Metal-Oxide-Semiconductor (CMOS) technologies sample the input signal usually several times over the Nyquist rate – between 8-512 times. As there is no one-to-one correspondence between the input and output signals – samples aren’t processed independently, as the converter uses preceding input samples to generate a valid output – there must be memory elements in the ADC structure. Oversampling converters have the disadvantage of needing a considerable amount of digital circuitry, however, with digital technology advancements, digital circuitry has become smaller and efficient, consuming less power and occupying less space, rendering this disadvantage negligible. Thus, in reality, while Nyquist rate converters can only achieve an relatively low Effective Number of Bits (ENOB) of around 10 bits but at really high frequencies, oversampling converters can achieve higher resolutions with a smaller bandwidth, trading speed of conversion for accuracy.

Therefore, this thesis presents the fine tuning and implementation of an ultra low power Multi-stAge Noise SHaping (MASH) 2+1 Switched-Capacitor (SC) Sigma-Delta Modulator (Σ∆M), working as an ADC, using passive integrators (resistor-capacitor (RC) branches) under Ultra Incomplete Settling (UIS) for audio applications – having a band-width of 20 kHz and ideally, an ENOB of 15 bits or above – heavily based on the work done by Fouto and Paulino in [2]. The

1.2 Contributions

This thesis shows that the implemented improvements to the MASH 2+1Σ∆M, ac-commodate the performance loss due to added parasitics by the circuit layout design and increase the overall corner stability of the circuitry. A layout design is created for the MASH 2+1 Σ∆M where each of the building block is tested and its performance evaluated.

The modifications done to the original MASH 2+1 Σ∆M implementation include: replacement of the ideal resistors and capacitors to real ones, addition of bias voltage compensation amplifiers to both amplifiers (G₂ and G_mid), passive integrator’s main capacitor value increase, removal of common-mode capacitors from the second order Σ∆M, increase to monostable’s pulse width, separation of circuit supply voltages (analog, mixed and digital), N-type Semiconductor (NMOS) and P-type Metal-Oxide-Semiconductor (PMOS) switch closed state resistance matching and reduction and finally, the addition of digital buffers to each of the produced phases that interacts with the main circuit. After the previously mentioned modifications, the MASH 2+1 Σ∆M achieves 86.755 dB of Signal-to-Noise-and-Distortion Ratio (SNDR) with 2 kHz, 300 mV input signal.

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1 . 3 . T H E S I S O R G A N I Z AT I O N

1.3 Thesis Organization

The chapters following the introduction describe the path taken into the implementa-tion of theΣ∆M-based ADC using UIS. The chapters are structured as follows:

• Chapter 2 -Σ∆ Modulation and Data Conversion Fundamentals

This chapter presents a brief history background of Σ∆ Modulation and signal conversion fundamentals.

• Chapter 3 - Architecture’s High Level Model

The architecture of theΣ∆M is presented in this chapter alongside it’s high level model, theoretical simulation using MATLAB® _{and its high level improvement.}

• Chapter 4 - Electrical Circuits, Layout and Simulation

This chapter presents the developed circuits to achieve the objective of this thesis, circuits layout design and schematic and circuit layout extraction level simulations. • Chapter 5 - Conclusions and Future Work

A discussion on the obtained results and conclusions for this work is performed, alongside suggestion for future work.

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Σ∆ Modulation and Data Conversion

F u n da m e n ta l s

In this chapter, an overview of the theoretical aspects addressed in this thesis is pre-sented, alongside some historical background on Sigma-Delta Modulators (Σ∆Ms). Then, the main concepts behind signal conversion are presented and discussed.

2.1 Σ∆ Modulation

Σ∆ modulation had its origins in ∆ modulation transmission techniques, invented by Deloraine et al. in 1946. In 1954, Cutler introduced the principles of oversampling and noise shaping with the intent of achieving higher resolution. Digitally heavy circuits weren’t usually implemented due to their complexity and associated cost at the time, a consequence of vacuum tube technology. At this point, transistors began to replace vacuum tube technology, which led Inose et al. to introduce the firstΣ∆M [6] in 1962. TheΣ∆M managed to experimentally achieve Signal-to-Noise Ratio (SNR) of about 35 dB with a sampling frequency of 7 kHz and a signal input with 30 Hz. This type of data conversion allowed trading speed for accuracy with the help of additional digital circuitry, which at the time was not developed, available and cheap enough to make this technology attractive for commercial use.

During the next decades, Candy described the first oversampling multibitΣ∆ Analog to Digital Converter (ADC) [7] embodying all the concepts ofΣ∆ Modulation such as noise shaping, digital filtering and decimation filter in order to achieve a higher resolution. Candy and An-Ni Huynh also proposed the Multi-stAge Noise SHaping (MASH) structure in 1986 [8]. Initially,Σ∆Ms were mainly used as ADCs in audio signals due to the required large Oversampling Ratio (OSR), coupled with the maximum clock frequency available at the time limiting the maximum signal bandwidth.

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Since then, research has improvedΣ∆M-based ADCs performance, achieving multi-MHz bandwidth with competitive SNR, Dynamic Range (DR), resolution and power when compared with other high bandwidth architectures. The use ofΣ∆M ADCs in Integrated Circuits (ICs) is becoming popular due to the offered advantages over other architectures in low frequency and high resolution applications. The main advantage nowadays was once its major disadvantage – its digitally intensive nature – due to advanced and matured Electronic Design Automation (EDA) tools for automated design and synthesis, allowing complex digital circuits with small footprint in die area and power consumption; this digital nature lets theΣ∆M more resilient against analog component mismatch.

2.2 Signal Conversion Fundamentals

This section presents the theoretical behaviour of ADCs. The analog input signal of the ADC is transformed into a bitstream, digitally representing the input signal at the output. An analog signal is a waveform that can assume infinite values in a finite time frame. So, sampling of the input signal is done at a constant period, T_s, this way converting an analog time based signal to a time independent digital signal with finite values at the output, as represented in Figure 2.1. Here x(t), s(t), y(t) and y(k) represent respectively, the analog input signal, sampling function with constant period, time discretized input signal (sampled input signal) and the amplitude discretized input signal (quantized input signal).

x(t) y(t) y(k)

s(t)

Quantizer

Figure 2.1: Sampling and quantization process.

The process of sampling in the time domain is illustrated in Figure 2.2, where the input signal, x(t), is multiplied by the sampling function, s(t), composed of periodic Dirac delta pulses described in Equation 2.1; the product is a time discretized version of the input signal where two consecutive samples are separated by a constant period,

Ts. Figure 2.2 does not illustrate the amplitude discretized signal as it depends on the

quantizer’s resolution. s(t) = +∞ X n=−∞ δ(t− nTs) (2.1)

The sampling process can be illustrated in the frequency domain after applying the

Fourier transform to the continuous time equations, resulting in the visuals presented in

Figure 2.2. The Fourier transform decomposes a signal into it’s frequencies. There is 6

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2 . 2 . S I G N A L C O N V E R S I O N F U N DA M E N TA L S

t x(t)

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An Ultra Low Power Amplifier-less Σ∆ Modulator

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DRAFT: 8 de Fevereiro de 2018

(a) Input analog signal.

t s(t)

Ts2Ts3Ts4Ts5Ts6Ts7Ts8Ts9Ts

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An Ultra Low Power Amplifier-less Σ∆ Modulator

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(b) Sampling function.

t y(t)

Ts2Ts3Ts4Ts5Ts6Ts7Ts8Ts9Ts

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An Ultra Low Power Amplifier-less Σ∆ Modulator

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(c) Unquantized sampled signal. Figure 2.2: Time domain sampling process.

a continuous time and a discrete time definition, as presented in Equation 2.2 and 2.3 respectively. ˆ f (ξ) = Z ∞ −∞f (x)e −2iπxξ_dx _(2.2) X_k= N−1 X n=0 x_ne−i2πkn/N _(2.3) The input signal in the frequency domain, Figure 2.3 (a), has a range of frequencies and the maximum signal frequency defines it’s bandwidth, designated by B. After apply-ing the Fourier transform on the samplapply-ing function, Equation 2.1, one can notice that periodic Dirac pulses in time domain are periodic Dirac pulses in the frequency domain, depicted in Figure 2.3 (b). S(jω) =2π Ts +∞ X k=−∞ δ ω− k2π Ts ! (2.4) Time domain multiplication of two signals is equivalent to the operation of convolu-tion in the frequency domain, originating Equaconvolu-tion 2.5 and resulting in spectral signal reproductions centred on integer multiples of the sampling frequency, f_s =1_/_T_s_{, as}

de-picted in Figure 2.3 (c). Y (jω) = 1 2πX(jω)⊗ S(jω) = 1 Ts +∞ X k=−∞ X jω−j2πk Ts ! (2.5) In Equation 2.5 the spectral signal repetitions directly depend on the sampling fre-quency. Thus, if the sampling frequency is too low the spectral repetitions will overlap themselves, originating an effect called aliasing. This means that high frequency spectrum components overlap the input signal spectrum, represented in black in Figure 2.4 (a). Af-ter aliasing occurs, one cannot recover the original signal due to the added distortion [9]. To avoid this effect, the Nyquist-Shannon Theorem [10] should be used, which states that a signal can be sampled without the loss of information if the sampling frequency, f_s, is two times or higher than the maximum signal frequency, B. This frequency is named Nyquist Rate and is defined in Equation 2.6.

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−B B f X(f )

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An Ultra Low Power Amplifier-less Σ∆ Modulator

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(a) Input signal spectrum.

−2fs −fs fs 2fs f

S(f )

Dimo Atanasov Naydenov

An Ultra Low Power Amplifier-less Σ∆ Modulator

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(b) Sampling function spectrum.

−2fs −fs −B B fs 2fs f

Y (f )

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An Ultra Low Power Amplifier-less Σ∆ Modulator

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(c) Sampled signal spectrum.

Figure 2.3: Frequency domain sampling process.

−4fs−3fs−2fs −fs fs 2fs 3fs 4fs f

Y (f )

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An Ultra Low Power Amplifier-less Σ∆ Modulator

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(a) Undersampling.

−2fs −fs −B B fs 2fs f

Y (f )

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An Ultra Low Power Amplifier-less Σ∆ Modulator

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(b) Oversampling. Figure 2.4: Over and under sampling in frequency domain.

F_N = 2 × B (2.6)

2.2.1 Analog-to-Digital Converter Structure

The basic principals of a general ADC can be directly applied toΣ∆M. A general ADC is composed by an Anti-Aliasing Filter (AAF), a Sample and Hold (S/H), a Quantizer and finally a Binary Encoder as depicted in Figure 2.5. The AAF is used before the sampling action to enforce a bandwidth limit to prevent aliasing. The time discretization is done by the S/H, which samples the continuous input signal at the sampling frequency, f_s. The quantizer provides an amplitude discretization of the time discretized input signal by mapping a continuous range of amplitudes of the input signal into a finite number of discrete levels. The binary encoder transforms each level from the previous actions into a unique binary code.

x(t) AAF f x1(t) fs S/H y(k) Quantizer y(k) Binary Encoder z

Figure 2.5: Generic block diagram for an ADC.

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2.2.2 Quantization

The amplitude discretization accomplished is also called quantization and is per-formed by the quantizer. The mapping between the continuous range of amplitudes of the input signal and the finite number of discrete levels of the quantizer is done by a staircase characteristic. The ideal staircase characteristic is depicted in Figure 2.6 (a). This amount of discrete levels of the staircase characteristic is exponentially dependent on the resolution of the quantizer. A N bit quantizer will provide 2N _{discrete levels. The}

difference between two consecutive quantized values (steps) is called step size – repre-sented by ∆ – and defined by the quantizer’s full scale range (Q_R) and the number of levels, as shown in Equation 2.7. The full scale range of the quantizer is the range of input amplitude where the output is not overloaded.

∆ = QR

2N_{− 1} (2.7)

The staircase characteristic of the quantization process is inherently lossy due to the mapping of the input value to the nearest corresponding amplitude level, making it impossible to recover the original signal. This difference between the original value and the quantized value is called quantization error, EQ, and is contained between ±∆/2

unless an overload of the quantizer happens as illustrated in Figure 2.6 (b). The overload happens when the amplitude of the input signal is outside the full scale range of the quantizer.

Input Output

∆

QR

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An Ultra Low Power Amplifier-less Σ∆ Modulator

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(a) Ideal staircase characteristic.

Input E_Q

∆_/2

−∆_/2

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An Ultra Low Power Amplifier-less Σ∆ Modulator

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(b) Quantization error. Figure 2.6: Ideal quantizer characteristics.

The quantization error can be modelled as white quantization noise if the input signal has a component with an amplitude around ∆ that is an independent random process. The average power of E_Q is obtained by averaging E2

Q over all possible values of EQ

(Equation 2.8). P_E_Q = 1 ∆ Z ∆/2 −∆_/₂ E_Q2 dE_Q=∆2 12 (2.8)

From Equation 2.8 is possible to conclude that the average power of EQ is directly

proportional to ∆. Thus, according to Equation 2.7, increasing the quantizer’s resolution, 9

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N , decreases the step size (∆), decreasing this way P_E_Q. For every additional bit in the quantizer’s resolution, PEQdecreases by 6.02 dB [9].

When the input signal is sampled at a frequency fs, the quantization noise is

dis-tributed uniformly between −fs/2andfs/2. From Equation 2.7 and 2.8, the Power Spectral Density (PSD) can be obtained according to Equation 2.9. Thus, increasing the sampling frequency (fs) will decrease the PSD, that is, the quantization noise will be spread out

over a wider frequency band reducing the in-band noise, as illustrated in Figure 2.7. This is one of the major advantages of using oversampling.

SQ(f ) = _f1 s× PEQ= 1 fs × ∆2 12 = ∆2 12 × fs (2.9) f SQ(f ) Nyquist rate Oversampling

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DRAFT: 15 de Fevereiro de 2018 Figure 2.7: Spectral density of quantization noise.

2.2.3 Oversampling

In digital audio applications high resolution and linearity is required. Typically Nyquist rate converters aren’t able to provide the needed accuracy. Oversampling con-verters as theΣ∆M ADCs can trade conversion time for resolution using large tolerance analog components with a digital output low pass filter [9]. The oversampling can be measured by an adimentional unit called OSR, defined in Equation 2.10.

OSR = fs

2 × B (2.10)

By integrating SQ(f ) (PSD) over the spectral bandwidth of the signal, the in-band

quantization noise power is described by Equation 2.11.

P_Q=Z B

−BSQ(f ) df =

∆2

12 × OSR (2.11)

From Equation 2.11, it is possible to conclude that, theoretically, every doubling of the OSR will increase SNR by 3 dB and consequently Effective Number of Bits (ENOB) by 0.5 bit. This behaviour was already illustrated in Figure 2.7.

2.2.4 Performance Metrics

Performance metrics allow the characterization and comparison of data converters. This metrics are generally classified into two categories: static or dynamic [11]. Firstly,

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the concept of Least Significant Bit (LSB) should be introduced, as it is a fundamental block for the performance metrics. LSB is the smallest value that can be represented by a quantizer or a converter and is defined as:

LSB =FSrange

2N (2.12)

where FSrangeif the full scale range of the unit – this can be a different unit according to

the data converter – and N is the resolution in bits. The static performance metrics are the following:

• Offset error – is the horizontal difference of the first transition level between the real and ideal value. This error is measures in LSB.

• Differential Non-linearity (DNL) – provides information about the converter’s non-linearity in a code by code manner and is measured in LSB. The DNL error is difference between the actual step size and the ideal value (1 LSB). In general DNL can have the following values and respective meanings:

DNL = 0 – two consecutive transitions are exactly 1 LSB apart. 0 < DNL <= 1 – monotonic transfer function with no missing codes. DNL > 1 – high probability of existing missing codes.

• Integral Non-linearity (INL) – provides information about the converter’s distor-tion in a code by code manner and is measured in LSB. The INL error is the deviadistor-tion of the converter’s transfer function and a straight line. It can also be defined as the cumulative sum of the DNL values.

The dynamic performance metrics are:

• Signal-to-Noise Ratio (SNR) – is the ratio between input signal and in-band noise power at the converter’s output. This measurement is input signal amplitude – A – dependent, so usually the best ratio is presented. It also does not take account Direct Current (DC) and harmonic components. If only the quantization noise power PQ

is considered, SNR is given by:

SN R = A2

2 × PQ

[dB] (2.13)

• Dynamic Range (DR) – is ratio between the maximum input signal amplitude when 3 dB below SN DR_peakis achieved, A_max, and the input signal amplitude when a 0 dB of SNR is achieved. For simplicity reasons, can be given by Equation 2.14.

DR = A

2

max

2 × PQ [dB] (2.14)

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• Total Harmonic Distortion (THD) – is the ratio between the fundamental fre-quency power and the sum of the power from all the harmonic frequencies above the fundamental.

• Signal-to-Noise-and-Distortion Ratio (SNDR) – is the ration between the input signal power and the power of all degradation elements, such as THD. As it is similar to SNR and takes into account THD, it can given as a function of those (Equation 2.15).

SN DR = 10T HD/10_{+ 10}−SN R_/10 _[dB] _(2.15)

• Effective Number of Bits (ENOB) – is the actual resolution achieved by the data converter in bit. This value is equal or smaller to the theoretical resolution and can be given by Equation 2.16. EN OB =SN DRpeak− 1.76 6.02 [bit] (2.16) A S N R, S N D R [d B ] 0 A_max A OL A_mi n S N Rpeak S N D Rp eak DR

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An Ultra Low Power Amplifier-less Σ∆ Modulator

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DRAFT: 18 de Fevereiro de 2018 Figure 2.8: Performance metrics.

To ease the data converter’s performance evaluation and comparison, a Figure of Merit (FoM) can be used. The FoM combines various performance metrics of the data converter to a single value. The most used ADC FoMs are the Walden FoM and the Schreier FoM, given by Equation 2.17 and 2.18 respectively.

FOM_W = P ower 2 × B × 2EN OB " J conv.− step # (2.17) FOMS= SN DR + 10 × log10 B P ower [dB] (2.18) 12

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2 . 3 . Σ∆ MODULATION BASICS

2.3 Σ∆ Modulation Basics

After the brief introduction to the world of data converters, the knowledge can be applied toΣ∆M ADCs. As mentioned before, oversampling converters such as Σ∆M ADCs need only simple AAFs, which in certain cases can be taken out altogether. As this work will be based on the use of Switched-Capacitor (SC) circuits there is no need for S/H circuitry. Thus, a simple representative block diagram for such an ADC is illustrated in Figure 2.9.

x(t) _Σ∆

Modulator y(k) BinaryEncoder z

Dimo Atanasov Naydenov

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An Ultra Low Power Amplifier-less Σ∆ Modulator

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DRAFT: 18 de Fevereiro de 2018 Figure 2.9: Block diagram for aΣ∆M ADC.

The two main types of oversampling converters are ∆ and Σ∆ modulators, which are closely related due to the fact thatΣ∆ modulation was derived from ∆ modulation, as explained in Section 2.1. The major disadvantage of the∆ modulator that led the development of theΣ∆M was that it amplified the in-band non-linear Digital to Analog Converter (DAC) distortion. To overcome this,Σ∆Ms implements a forward path loop filter [9]. A block diagram of a basic first order Discrete Time (DT)Σ∆M is illustrated in Figure 2.9. x(kTs) _Integrator u(kTs) ADC y(kTs) q(kT_s) DAC

-(a) First orderΣ∆ modulator.

X(z) H(z) E_Q(z) Y (z) -Q(z)

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(b) First orderΣ∆ modulator’s z-domain linear model.

Figure 2.10: Block diagram for a first orderΣ∆ modulator.

A basic first orderΣ∆M is constituted by an integrator, a 1-bit ADC and a 1-bit DAC for feedback purposes. In this case, the 1-bit ADC is a comparator that quantizes it’s

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input into two levels. The 1-bit DAC feeds back one of two values of references according to the comparator’s output.

In order to analyse the behaviour of the circuit, it is necessary to obtain the linearized model of the Σ∆M shown in Figure 2.10 (a), allowing one to obtain the output signal expression. Firstly, one can obtain the expression for the output of the integrator, Equa-tion 2.19.

u[kTs] = x[(k − 1)Ts] − q[(k − 1)Ts] + u[(k − 1)Ts] (2.19)

The quantization error of the 1-bit ADC is defined as the difference between it’s output and input, Equation 2.20.

EQ[kTs] = y[kTs] − u[kTs] (2.20)

Assuming an ideal 1-bit DAC (a unity gain block), it’s output will be equal to it’s input, Equation 2.21.

q[kT_s] = y[kTs] (2.21)

Thus, from the previous expressions, the output of the first orderΣ∆M can be defined as:

y[kT_s] = x[(k − 1)Ts] + EQ[kTs] − EQ[(k − 1)Ts] (2.22)

TheΣ∆M’s quantization noise cancellation is evident in Equation 2.22. The output is the input signal value delayed by one sampling period (Ts) plus the difference the current

quantization error and the previous quantization error. This means that the quantization noise cancels itself to the first order at DC [9, 12].

Figure 2.10 (b) illustrates the ideal frequency domain model of the modulator. To model a DTΣ∆M, in the frequency domain, z-transform is needed. In the z-domain an ideal transfer function of an integrator is1_/_z₋₁_{, the quantizer is assumed as an}

quantiza-tion error source, EQ(z), and the 1-bit DAC is modelled as an unity block (not need to

represent). This way, the output of theΣ∆M in the z-domain is given by Equation 2.23.

Y (z) = z−1X(z) + (1− z−1)EQ(z) (2.23)

Equation 2.23 shows the output of theΣ∆M depending only on the input signal and the quantization noise. The expression multiplied by the input signal is called Signal Transfer Function (STF) and the expression multiplied by the quantization noise is called Noise Transfer Function (NTF). Thus, Equation 2.23 can be rewritten as Equation 2.24. Figure 2.11 illustrates the frequency response of both STF and NTF.

Y (z) = ST F(z)X(z) + N T F(z)E_Q(z) (2.24) The generic form of the STF and the NTF is given in Equation 2.25.

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2 . 3 . Σ∆ MODULATION BASICS

ST F(z) = H(z)

1 + H(z) N T F(z) = 1

1 + H(z) (2.25)

To illustrate STF’s and NTF’s behaviour, one can use the equivalence z = ej2πf_{, then}

plot |ST F(ej2πf )_|2_{and |NT F(e}j2πf )_|2_{, as shown in Figure 2.11. The frequency on the plot}

is normalized –f_/_f_s _{– in order to be generic.}

B fs/2 1 2 3 4 Normalized frequency (f_/_f_s₎ Magnitude |ST F(ej2πf_)|2 |NT F(ej2πf_)|2

Figure 2.11: Frequency response of ST F and N T F for a first orderΣ∆M.

From Figure 2.11 is possible to verify that the first order noise shaping takes place, that is, as the OSR gets higher, the quantization noise is heavily attenuated and moved into out-of-band frequencies. At the output of theΣ∆M ADC, a decimation filter (usually based on cascaded sync filters) must be used as a low-pass filter and a downsampler [9].

The in-band noise power of the modulator’s output can be calculated by integrating |NT F(ej2πf_)|2_{multiplied by PSD (Equation 2.9), originating Equation 2.26.}

PIBN = Z 1/2×OSR 0 |NT F(e j2πf_)|2_× ∆2 12 × fs df = ∆2 12 × π2 3 × (OSR)3 (2.26)

The peak SNR for a full-scale input signal and a N bit quantizer is given by Equa-tion 2.27 [9].

SN R_peak= 3 × N2× (OSR)3

2π2 [dB] (2.27)

According to Equation 2.27, the SNR increases with a factor of 8 – ∼9 dB – every time the OSR is doubled, resulting in a 1.5 bit increase in ENOB in comparison with only 0.5 bit when using only oversampling.

Second orderΣ∆Ms increases the noise shaping by adding another integrator in the loop as shown in Figure 2.12. One can still identify the first order loop. The main difference between first and second order loops besides the additional integrator is the change in the transfer function of one of the integrators. The first integrator has the same

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transfer function as discussed before – H1(z) =1/1−z−1 – but the transfer function of the

second integrator has an added delay – H2(z) =z−1/1−z−1.

x(kT_s)

Integrator Integrator ADC y(kTs)

q(kT_s)

DAC

-

-1stOrderΣ∆M

(a) Second orderΣ∆ modulator.

X(z) H1(z) H2(z) EQ(z) Y (z) Q(z) - -1st_Order_Σ∆M

(b) Second orderΣ∆ modulator’s z-domain linear model.

Figure 2.12: Block diagram for a second orderΣ∆ modulator.

The output expression is obtained similarly as before, originating Equation 2.28.

y[kTs] = x[(k − 1)Ts] + EQ[kTs] − 2 × EQ[(k − 1)Ts] + EQ[(k − 2)Ts] (2.28)

Using the z-transform on Equation 2.28, result in Equation 2.29.

Y (z) = z−1X(z) + (1− z−1+ z−2)EQ(z) = z−1X(z) + (1− z−1)2EQ(z) =

= ST F(z)X(z) + N T F(z)EQ(z)

(2.29) Comparing Equation 2.23 and Equation 2.29, the STF in the latter has not changed while NTF has been squared. After plotting |ST F(ej2πf )_|2_{and |NT F(e}j2πf )_|2_{, Figure 2.13,}

is possible to notice that the signal is not affected, while the in-band quantization noise is more attenuated and is even more amplified at higher frequencies when compared to a first orderΣ∆M. Although there is more quantization noise, as it is located at higher frequencies, it can be easily filtered by a decimation filter at the output.

Similarly to the first orderΣ∆M, with the same considerations, the second order Σ∆M has an in-band noise power defined by Equation 2.30 and a SNR defined by Equation 2.31.

PIBN= Z 1/2×OSR 0 |NT F(e j2πf_)|2_× ∆2 12 × fs df = ∆2 12 × π4 5 × (OSR)5 (2.30) 16

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2 . 3 . Σ∆ MODULATION BASICS B fs/2 2 4 6 8 10 12 14 16 Normalized frequency (f_/_f_s) Magnitude |ST F(ej2πf_)|2 |NT F(ej2πf_)|2

Figure 2.13: Frequency response of ST F and N T F for a second orderΣ∆M.

SN R_peak= 5 × N2× (OSR)5

2π4 [dB] (2.31)

When using a second order_{Σ∆M, the SNR increases with a factor of 32 – ∼15 dB –} every time the OSR is doubled, resulting in a 2.5 bit increase in ENOB in comparison with only 0.5 bit when using only oversampling and 1.5 bit when using a first orderΣ∆M. There must be once more a decimation filter at the output of theΣ∆M for filtering and downsampling.

To create higher orderΣ∆Ms, more integrators can be added to the first order Σ∆M structure, offering this way higher noise shaping order resulting in higher resolution and additional attenuation of the in-band quantization noise while maintaining OSR. Higher orderΣ∆Ms have stability issues as this structure uses feedback loops [9, 12]. If stable, higher orderΣ∆Ms offer a NTF given by Equation 2.32 and a in-band quantization noise power given by Equation 2.33, where L represents the order of the loop.

N T F(z) = (1− z−1)L _(2.32) P_IBN = Z 1/_2×OSR 0 |NT F(e j2πf_)|2_× ∆2 12 × fs df = ∆2 12 × π2×L (2 × L + 1) × (OSR)2×L+1 (2.33)

To overcome the shortcomings of higher orderΣ∆Ms, multi-stage structures can be used, like Leslie-Singh Structure [13] and the already mentioned MASH [8] structure, the latter being used in this work. Instead of trying to filter the quantization noise, this structure tries to cancel it by the use of easy to implement lower orderΣ∆Ms while achieving the same order of noise shaping.

The MASH structure is implemented using two or more stages ofΣ∆Ms, where the quantization noise – that is, the difference between output and input of the quantizer – of

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the current stage is the input signal of the following stage. The outputs of each stage are then digitally filtered and summed in such a way that only the quantization noise of the last stage is not cancelled. The naming scheme for MASH structures usually composed by the word MASH followed by string of number separated by the + sign, for example, MASH 1+1. This indicates that there are 2 stages in the structure, each being a first order Σ∆M. A generic example of a MASH 1+1 is illustrated in Figure 2.14.

X _Integrator _Quantizer Y1 - H1 Y -Integrator Quantizer Y2 - H2 -EQ1 EQ2 Digital Cancellation Logic Figure 2.14: Block diagram for a MASH 1+1Σ∆M.

The output of each stage shown in Figure 2.14 is given by Equation 2.34 and Equa-tion 2.35.

Y1(z) = ST F1(Z)X(z) + N T F2(z)EQ1(z) (2.34)

Y2(z) = ST F2(Z)EQ1(z) + N T F2(z)EQ2(z) (2.35)

The blocks H1and H2 are part of the Digital Cancellation Logic (DCL) designed to

cancel the quantization error of the first stage by fulfilling the following condition:

H1(z) × NT F1(z) = H2(z) × ST F2(z) (2.36)

Admitting that H1(z) = ST F2 and H2= N T F1, the MASH structure output can be

given by:

Y (z) = H1(z)Y1(z) − H2(z)Y2(z) =

= ST F1(z)ST F2(z)X(z) − NT F1(z)N T F2(z)EQ2(z)

(2.37) Using the previously obtained expressions for a first orderΣ∆M’s STF and NTF on Equation 2.37, originates Equation 2.38.

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2 . 4 . L O W P O W E R Σ∆ MODULATORS

Y (z) = z−2X(z)− (1 − z−1)2EQ2(z) (2.38)

From this information, it can be concluded that the NTF is exactly the same as an usual second orderΣ∆M, although in this case the input signal is delayed by two samples. In theory, this principle can be extended to several stages, although each additional stage introduces less benefits. Usually this type of structures goes to a maximum of three stages. The stability of the structure depends on the stability of each stage because there are only feedforward paths between the stages, yielding this way a clear advantage over same order single-loopΣ∆Ms.

A major drawback of MASH structures is their sensitivity to mismatching between the analog and digital transfer functions, that is, modulator’s and the DCL’s transfer functions.

2.4 Low Power Σ∆ Modulators

In this section, the main techniques used in the literature to achieve high accuracy and high performanceΣ∆Ms while also maintaining a low power consumption will be presented.

2.4.1 Low Power Techniques

With the introduction of ever smaller transistor feature size, the achievement of high performance low power circuitry has become harder. This is due to the fact that with smaller transistor feature size, come lower power supply voltages and smaller transistor intrinsic gain. Thus making it harder to build high-precision analog circuits, which performance often depends on the quality of the virtual grounds (i.e. matching between two transistors) [14]. On the other hand, smaller feature size introduces smaller parasitics, allowing higher frequency circuits.

OversamplingΣ∆M ADCs can be divided into their analog and digital parts. As dis-cussed before, digital components are as energy efficient as the technology allows, which does not allow space for improvement. The analog components – mainly the amplifiers – on the other hand, represent the vast majority of the ADC’s power consumption when

using active integrators.

To fight the power consumption by the analog components, one can use a smaller number of amplifiers by sharing the amplifier in a time interleaved fashion across mul-tiple active integrators [15, 16], thus decreasing the power consumption by eliminating components. While using lower number of amplifiers, it is possible to achieve higher or-der noise shaping using complex feedback schemes that may include feedforward paths (positive feedback) [15]. Another way to achieve lower power consumption by the analog blocks would be the use of Inversion Coefficient (IC) based methodology during design phase.

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Power savings can also be brought through the use of passive or active-passive archi-tectures, that is, using passive integrators, where the quantizer provides the majority of gain for the feedback loop [17]. To maintain independence and avoid negative effects between passive integrators, there must be a simple gain stage between integrators for isolation. This can be provided by simple low gain amplifiers [1, 18], with the benefit of extra gain in the loop filter.

2.4.2 Passive Σ∆M

PassiveΣ∆Ms can be implemented in Continuous Time (CT) or Discrete Time (DT) by using a low pass filter in place of the active integrator. A passive CTΣ∆M is presented in [18], where the integrators are implemented through first order resistor-capacitor (RC) cir-cuits, illustrated in Figure 2.15, with either only a pole or a pole and a zero, Figure 2.15 (a) and (b) respectively.

Vin

R1

Vout

C₁

(a) Single pole.

V_in R2 V_out

C1

R₁

(b) Single pole and zero. Figure 2.15: CT passive RC integrator.

The passive RC integrators in Figure 2.15 have respectively, transfer functions de-scribed in Equation 2.39 and 2.40.

H(s) = 1

1 + sR1C2 (2.39)

H(s) = 1 + s(R1C1)

1 + s(R1+ R2)C2 (2.40)

In [18], two gain blocks were added to the loop to avoid the loading effect on the following stage and provide extra gain in the loop as mentioned before. Thus, theΣ∆M is able to achieve 69.1 dB of SNDR, 76.2 dB of DR with a bandwidth of 2 MHz, while consuming 256 µW at 0.7 V, proving the high energy efficiency of CT passive integrators.

DT passive integrators usually are implemented as a first order RC filter where a SC branch replaces the resistor, as illustrated in Figure 2.16. Chen and Leung use passive SC integrators to implement the loop filter of aΣ∆M in [19], achieving 77 dB of SNDR, 87 dB of DR with 20 kHz bandwidth and a power consumption of 230 µW.

This SC passive integrator has a transfer function defined by Equation 2.41. 20