Optoelectronic modules for next generation optical networks

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Universidade de Aveiro Departamento deElectrónica, Telecomunica¸cões e Informática, 2017

Ricardo Jorge

Mendon¸

ca Coelho

M´

odulos ´

otico-eletr´

onicos para redes ´

oticas de

futura gera¸

c˜

ao

Optoelectronic modules for next generation optical

networks

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Universidade de Aveiro Departamento deElectrónica, Telecomunica¸cões e Informática, 2017

Ricardo Jorge

Mendon¸

ca Coelho

M´

odulos ´

otico-eletr´

onicos para redes ´

oticas de

futura gera¸

c˜

ao

Optoelectronic modules for next generation optical

networks.

Disserta¸cão apresentada à Universidade de Aveiro para cumprimento dos requisitos necessários à obten¸cão do grau de Mestre em Engenharia Electrónica e Telecomunica¸cões, realizada sob a orienta¸cão cient´ıfica de Dr. Mário Lima, Professor do Departamento de Electrónica, Telecomunica¸cões e Informática da Universidade de Aveiro e Engenheiro Francisco Rodrigues, PICadvanced, SA.

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Dedico este trabalho aos meus pais e restante fam´ılia

sempre pr´

oxima de mim.

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o j´uri / the jury

presidente / president Professor Doutor Paulo Miguel Nepomuceno Pereira Monteiro Professor Associado da Universidade de Aveiro

vogais / examiners committee Professor Doutor M´ario Jos´e Neves de Lima Professor Auxiliar da Universidade de Aveiro (orientador)

Professor Doutor Henrique Manuel de Castro Faria Salgado Professor Associado da Universidade do Porto

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agradecimentos Come¸co por agradecer à PICadvanced, SA por me ter proporcionado a opor-tunidade de realizar estre trabalho e ter disponibilizado todos os recursos pedidos, bem como pelo ambiente de trabalho e empenho que me foi ensi-nado pelos membros da empresa aos quais também agrade¸co. Um especial agradecimento ao engenheiro José Lima pelo apoio técnico que me deu durante esta fase.

Ao Professor Mário Lima e ao engenheiro Francisco Rodrigues pela ori-enta¸cão na disserta¸cão, e por todos os conhecimentos técnicos que me transmitiram.

Ao Instituto de telecomunica¸cões por todos os recursos que me propor-cionou, em especial ao Professor António Teixeira e restantes membros do grupo de Ótica por me deixarem tanto à vontade nesta área e criarem um espa¸co para aprender mais e melhor.

`

A Funda¸cão para a Ciência e Tecnologia por me ter permitido participar no projeto FutPON e financiado com uma bolsa de investiga¸cão.

`

A minha fam´ılia que me acompanhou durante estes anos todos e sempre me apoiou nos bons e maus momentos e por isso lhes agrade¸co imenso. Aos colegas que fizeram parte da minha vida nos últimos anos. Alguns já partiram para longe, outros ainda estão por perto, mas todos foram marcantes para o meu caminho e para a minha experiencia de vida. Um abra¸co a todos.

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palavras chave Comunica¸c˜oes ´Oticas, NG-PON2, Transceiver, Optoeletronica

Resumo Nos últimos anos tem-se verificado uma clara evolu¸cão na implementa¸cão e desenvolvimento da fibra ótica até ao consumidor final. As redes Fiber-to-the-Home (FTTH) foram desenvolvidas e normalizadas em todo o mundo, no entanto, a necessidade de largura de banda pelos utilizadores e pe-los novos servi¸cos obrigou esta tecnologia a evoluir, desde as Gigabit-capable Passive Optical Networks (GPON) e 10 Gigabit-Gigabit-capable Passive Optical Network (XG-PON) para a Next Generation Passive Optical Net-work 2 (NG-PON2), que vai come¸car agora a sua implanta¸cão.

Para garantir a interoperabilidade entre operadores dentro da mesma tec-nologia, foram desenvolvidas normas para os componentes optoelectrónicos onde as suas interfaces e mecanismos de comunica¸cão são transparentes aos aparelhos que estão distribu´ıdos ao longo da rede permitindo assim a um operador utilizar produtos de diversos vendedores sem ter que adaptar a sua solu¸cão. Para as redes de acesso Passive Optical Networks (PON) de futura gera¸cão estes componentes têm que ser desenvolvidos, desde os componentes óticos inclu´ıdos nos transrecetores optoelectrónicos até os sis-temas eletrónicos de controlo dos mesmos.

O aumento da procura de optoelectrónica para tecnologias futuras cria uma necessidade de solu¸cões eletrónicas que possibilitem testar a sua opera¸cão e validar resultados e conformidades com as normas estabelecidas. Para transrecetores de nova gera¸cão é relevante a cria¸cão de solu¸cões que per-mitam testar a sua emissão e rece¸cão a altos ritmos de dados, bem como a reprograma¸cão manual ou automática dos seus paramentos eletrónicos, para otimiza¸cão dos pontos de opera¸cão, durante o seu processo de fabrico. Neste trabalho, apresentam-se componentes óticos de nova gera¸cão e introduz-se módulos inovadores no mercado que permitam de forma rápida e comoda programar, testar e caracterizar componentes óticos. Através dos módulos desenvolvidos, procede-se à caracteriza¸cão de componentes para redes de acesso de próxima gera¸cão em arquitetura NG-PON2.

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keywords Optical Communications, NG-PON2, Transceiver, Optoelectronics

Abstract Over the recent past, there has been a clear evolution in the development and implementation of fiber optics to the end user. FTTH networks were developed and normalized across the world, but the bandwidth requirements by users and services demanded that this technology evolved, from GPON to XG-PON, and now to NG-PON2, which is now starting its implementation. To ensure the functionality of a technology across different operators, stan-dards for optoelectronic components were developed, where their interfaces and communication mechanisms are transparent to the devices distributed in the networks, allowing an operator to use products from different ven-dors without the need to change the solution. For next generation PON access networks, these components need to be developed, from the optical components in the transceivers to their electrical control systems.

The rising demand for optoelectronics in future technologies creates a need for electronic solutions in testing operation performance, results val-idation, and compliance with established standards. For next generation transceivers, it is relevant to create solutions that allow to test both trans-mission and reception ate high data rates, allow manual or automatic repro-gramming of electronic parameters, for operation point optimization, during the manufacturing process.

On this work, next generation optical components are presented and innova-tive modules that allow quick and easy programing, testing and characteri-zation of optical components are introduced. Using the developed modules, a characterization is made on state of the art access network components for the NG-PON2 architecture.

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List of Figures

1.1 FSAN’s NG-PON roadmap. . . 2

2.1 TWDM-PON system diagram . . . 6

2.2 SFP module schematic. . . 7 2.3 XFP module schematic. . . 7 2.4 Two SFP+ modules. . . 8 2.5 CFP mechanical schematic. . . 8 2.6 QSFP module rendering. . . 9 2.7 GBIC module. . . 9 2.8 X2 module. . . 10 2.9 CXP form-factor module. . . 10 2.10 SFF module. . . 10

2.11 40 Gb/s 300-pin module schematic. . . 11

2.12 ST type connector. . . 12

2.13 SC type family connectors. . . 13

2.14 LC type duplex connector. . . 13

2.15 MTRJ type connector. . . 14

2.16 FC type connector. . . 14

2.17 Exemple of a structure transparent to a certain wavelength and reflective to others. 16 2.18 Schematic of generic tunable laser. . . 17

2.19 Simple driving circuit. . . 18

2.20 Variation of bias and modulation to compensate a change in temperature. . . 18

3.1 Project Block Diagram. . . 22

3.2 Schematic for the positive voltage sources. . . 24

3.3 Schematic for the negative power sources. . . 25

3.4 Schematic for USB converting circuit. . . 26

3.5 PWM circuit design in SPICE. . . 27

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3.7 PWM design in the board schematic. . . 29

3.8 PWM circuit simulation. . . 29

3.9 PWM circuit output simulation. . . 30

3.10 Main schematic. . . 30

3.11 TX-LINE results. . . 34

3.12 Saturn PCB design results. . . 35

3.13 POLAR Instruments results. . . 35

3.14 POLAR Instruments results for USB lines. . . 36

3.15 Drill Drawing. Y shapes are vias limiting the high-speed lines. On the right side, there are vias limiting the board’s edge. . . 37

3.16 Top view of the PCB. Metallic pads are present in the areas are still not assembled. 38 3.17 Tx signal testing setup. . . 39

3.18 Rx signal testing setup. . . 39

3.19 Eye diagram results for the transmissions tests. . . 40

3.20 Eye diagram results for the reception tests. . . 41

4.1 Block Diagram of the four-layer multiple XFP transceiver. . . 44

4.2 Interface with +12 V plug. . . 45

4.3 Positive 5 V power source. . . 45

4.4 Positive +3.3 V, +3.1 V and +3.5 V power source. . . 46

4.5 -5 V power source. . . 47

4.6 Control LED circuits. . . 48

4.7 Power input filters. . . 48

4.8 POLAR Instruments results. . . 49

4.9 Top view of the pcb design. . . 50

5.1 Block Diagram of the SFP programing board. . . 52

5.2 Power source block. . . 53

5.3 Power source simulation in WEBENCH. . . 53

5.4 Power source simulation in WEBENCH with a fitted axis. . . 54

5.5 Main circuit of the board. . . 54

5.6 Bottom layer of the board with red as +5.5 V plane, blue as +3.3 V plane and brown as ground plane. . . 55

5.7 Top layer of the baord with blue as 3.3V plane and brown as ground plane. . . . 56

5.8 3D model of the base. The model was 3D printed and install with the board. . . 57

6.1 PICadvanced user interface used to configure parameters. . . 60

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6.3 BER for channel 1. . . 63

6.7 TX tuning time measurments setup. . . 64

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List of Tables

2.1 NG-PON2 upstream and downstream channels. . . 15 2.2 NG-PON2 tuning time classes. . . 17 3.1 Texas Instruments recomended values for the feedback resistors and output filter

for the TPS54327 IC. . . 25 3.2 Power supply pinout . . . 31 3.3 I2C pinout . . . 31 3.4 High speed lines pinout . . . 31 3.5 High speed lines pinout . . . 32 3.6 Stackup Parameters - XFP two-layer design. . . 33 4.1 Stackup Parameters - Four layer design. . . 50 5.1 Stackup Parameters - SFP programing design. . . 56 6.1 NG-PON2 upstream channels. . . 59 6.2 Transceiver channel results. . . 62 6.3 Deviation between the testing boards and the professional network system. . . . 64 6.4 Transmission tuning times in milliseconds. . . 65 6.5 Results for reception tuning times. . . 66

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Acronyms

BEN Burst Enable

BER Bit Error Ratio

CFP C Form Pluggable

ER Extinction Ratio

FC Ferrule Connector

FSAN Full Service Access Network FTTH Fiber-to-the-Home

FTTP Fiber-To-The-Premises

FTTx Fiber To The X (home, business, etc.) GBIC Gigabit Interface Converter

GPON Gigabit-capable Passive Optical Networks I2_C _{Inter-Integrated Circuit}

IC Integrated circuit

ITU-T International Telecommunication Union - Telecommunication Standardization Sector

LC Lucent Connectors

LED Light Emitting Diode

MTRJ Mechanical Transfer Registered Jack

MOSFET Metal Oxide Semiconductor Field Effect Transistor MSA Multi-Source Agreement

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NG-PON Next Generation Passive Optical Network NG-PON2 Next Generation Passive Optical Network 2 OCDMA-PON Optical Code Division Multiple Access PON OEC Optical to Electrical Converter

OLT Optical Line Terminal ONU Optical Network Unit

OFDM-PON Orthogonal Frequency Division Multiplexed PON OSA Optical Spectrum Analyzer

PCB Printed Circuit Board PON Passive Optical Networks PWM Pulse Width Modulation

QSFP Quad Small Form-Factor Pluggable

SC Subscriber Connectors

SFF Small Form Factor

SFP Small Form Pluggable

SFP+ 10 Gigabit SFP

SMA SubMiniature version A

SNIA Storage Networking Industry Association ST Straight Tip Connector

TDM Time Domain Multiplexed TEC Thermoelectric Cooler

TWDM-PON Time and Wavelength Division Multiplexed PON USB Universal Serial Bus

VOA Variable Opical Attenuator

XFP 10 Gigabit Small Form Factor Pluggable XG-PON 10 Gigabit-capable Passive Optical Network

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WDM-PON Wavelength Division Multiplexed PON WM Wavelength Multiplexer

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Chapter 1

Introduction

This chapter introduces the scope and targets of this work. Section 1.1 presents, in the context of the current technology, the motivation for this dissertation. Section 1.2 exposes the main objectives of this work. Right after, Section 1.3 presents the structure of the dissertation and lastly, Section 1.4 lists the major contributions.

1.1 Motivation

FTTH architectures based on a PON is considered to be the ultimate goal of the access networks, since there are no limitations on both bandwidth and transmission length, contrary to copper based networks[1].

PONs have been widely-deployed worldwide. This is driven by the increasing bandwidth requirements from costumers[2], and studies predict ever lowering prices for Fiber-To-The-Premises (FTTP) deployments[3].

Nowadays, GPON is the most widely spread Fiber To The X (home, business, etc.) (FTTx ) access network technology in western countries. GPON is capable of transmitting 2.5 Gb/s in the downstream direction and 1.25 Gb/s in the upstream direction[4].

The same institution that defined the standard for GPON, the International Telecommu-nication Union - TelecommuTelecommu-nication Standardization Sector (ITU-T), realizing that the data rates would soon not be sufficient to meet demands, started working on a new PON standard called XG-PON. Defined in ITU-T norm G.987.1[5], XG-PON is capable of data rates in the order of 10 Gb/s for downstream and 2.5 Gb/s for upstream, and is able to coexist with GPON. The Next Generation Passive Optical Network (NG-PON) task group of the Full Service Access Network (FSAN) group planned a roadmap for the deployment of PON networks and actively present specifications to appropriate standardization bodies. In figure 1.1, presented below, an example of a FSAN roadmap is shown, where the next clear goal is the future deployment of a NG-PON2 network.

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Figure 1.1: FSAN’s NG-PON roadmap[6].

With this context, one can understand that companies in the telecommunication hard-ware development field are now targeting solutions for NG-PON2 hardhard-ware like, for example, transceivers capable of NG-PON2 operation. It is then relevant to create business targeted electronic modules for optical transceiver tests, with the intent to aid in the development of new components and testing already developed ones. This work proposes modules to fill these requirements for NG-PON2 transceivers.

1.2 Objectives

The main objective of this dissertation is the development of electrical modules to help in the development and testing of optical transceivers in NG-PON2. The defined objectives for this works are as follows:

• Introduce optical access network architecture in NG-PON2.

• Present the current solutions for optical transceivers and components in the market, and select which are the most relevant for NG-PON2.

• Design and produce a compact and cheap testing board for NG-PON2 10 Gigabit Small Form Factor Pluggable (XFP) transceiver.

• Design and produce a testing board for multiple XFP transceivers in NG-PON2.

• Design and produce a compact programing board for Small Form Pluggable (SFP) transceivers. • Use the previous boards to fully characterize and test the compatibility of a PICadvanced

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1.3 Structure

This dissertation is, excluding the present chapter, divided into 6 parts as follows:

• Chapter 2 - Transceivers for Next Generation Optical Networks presents to the reader the optical component and transceiver solutions available and introduces future optical access network architecture NG-PON2. The final part of the chapter explains what is expected from the figures of merit in a NG-PON2 transceiver.

• Chapter 3 - Testing board for next generation transceivers introduces the design of the schematic and Printed Circuit Board (PCB) of the XFP testing board.

• Chapter 4 - Four-layer Multiple Transceiver Testing Board presents the schematic and PCB layout of the multiple XFP testing board.

• Chapter 5 - Programing board for SFP transceivers shows the design of the schematic and PCB layout for the SFP programing board.

• Chapter 6 - Characterization of a Transceiver for NG-PON2 explains the process of characterization in a NG-PON2 architecture and presents the full testing results of a PICadvanced optical transceiver.

• Chapter 7 - Conclusions and Future Work presents a description of what was achieved, as well as the main conclusions taken from this work. Suggestions for more work in this topic are also presented.

1.4 Contributions

The main contributions of this work are:

• Development of two testing modules in use at PICadvanced.

• Incorporation of testing modules at a PICadvanced partner company.

• Development of a programing board introduced at the fabrication process in PICadvanced. • Contributions to the FutPON project, supported under by the European Structural

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Chapter 2

Transceivers for next generation

optical networks

On this chapter, the NG-PON2 architecture for PON is presented in 2.1. As optical transceivers are at the center of PON deployments, the optoelectronic components of opti-cal transceivers are explained and possible solutions are pointed out for use in future networks over sections 2.2 and 2.3.

Section 2.4 all relevant figures of merit in a NG-PON2 transceiver.

2.1 40-Gigabit-capable PON (NG-PON2)

The standard for NG-PON2 was defined by ITU-T in norm G.989.1[7] as a network archi-tecture fully capable of coexistence with both GPON and XG-PON modules in the same access network and with data rates of 40 Gb/s for downstream and 10G Gb/s for upstream with capability for 40 Gb/s symmetrical rate in both directions, 40 km reach and 1:64 split ratio.

Several technologies were proposed for NG-PON2 such as Wavelength Division Multiplexed PON (WDM-PON), Optical Code Division Multiple Access PON (OCDMA-PON), Orthogonal Frequency Division Multiplexed PON (OFDM-PON) and Time and Wavelength Division Mul-tiplexed PON (TWDM-PON)[8]. The later has attracted the majority of the support from global vendors and was selected by the FSAN community in the April 2012 meeting as a pri-mary solution to NG-PON2[9]. Figure 2.1 shows a network in TWDM-PON.

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Figure 2.1: TWDM-PON network diagram[8]

On a TWDM-PON architecture, four XG-PON networks are stacked by using four pairs of wavelengths. For simple network deployment and inventory management purposes, the Optical Network Unit (ONU) uses colorless tunable transmitters and receivers. The tunable transmitter is tunable to any of the four upstream wavelengths. The receiver is tunable to any of the four downstream wavelengths[8]. Options to the baseline architecture include more pairs of wavelengths and different rates for stacking. For example, TWDM-PON could support eight pairs of wavelengths[9]. Also, NG-PON2 must safeguard the use of legacy technologies with its wavelength allocation[8]. The wavelengths in use for NG-PON2 will be explained in more detail in section 2.5.

2.2 Transceiver modules

Optical transceivers are standardized modules composed of a transmitter, a receiver and the necessary electrical circuits to operate them.

The Small Form Factor (SFF) committee, now part of the Storage Networking Industry As-sociation (SNIA) made the effort to standardize the transceiver rates, form factor and electrical interfaces under a Multi-Source Agreement (MSA). This allows to simplify network upgrades or repairs as the modules are all standardized, and leads to faster industry development as the different manufacturers are not trying to compete with their individual standards and compat-ibility between different products is not lost.

The most widely used modules in modern PONs are the SFP, 10 Gigabit SFP (SFP+) and the XFP.

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2.2.1 SFP

The first standardized Transceiver module. SFP is capable of data rates up to 4 Gb/s and is designed to be compact, hot-pluggable and easy to handle and replace. The MSA schematic for a SFP transceiver is presented in figure 2.2.

Figure 2.2: SFP module schematic[10].

2.2.2 XFP

XFP was the first module to allow 10 Gb/s transmission rate. It is a larger module than the SFP, it is also designed to be hot-pluggable and easy to handle and replace.

XFP modules were standardized for point-to-point systems, but modules for point-to-multipoint, like PON systems, also exist. The MSA schematic for a XFP transceiver is presented in figure 2.3.

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2.2.3 SFP+

With the rise of data usage, the classic SFP module does not keep up with the need for a higher data rate SFP. SFP+ was developed as the result, designed to have the same size and fit on systems ready for SFP, while having a 10 Gb/s data rate.

SFP+ modules, much like the XFP ones, also have standards for point-to-multipoint sys-tems. An exemple of a SFP+ transceiver is shown in figure 2.4.

Figure 2.4: Duplex SFP+ module[12].

2.2.4 Other Transceiver modules

The following transceivers are relevant to understanding the current state of the market, but are not used to deploy PON architectures.

C Form Pluggable (CFP): A hot-pluggable optical transceiver operating at 40 Gb/s and 100 Gb/s. As technology improved, higher density modules were designed like CFP2 and CFP4 which are regular CFP modules but designed with a form-factor of 2 and 4 respectively. Due to de different form-factors, these modules are not interchangeable.

CFP8 is not yet covered under a multi-source agreement but a 400 Gb/s solution is under review. This proposed CFP8 is about the same size as the CFP2 module but has four times the bitrate[13]. Figure 2.5 shows a MSA schematic for CFP transceivers.

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Quad Small Form-Factor Pluggable (QSFP): Hot-pluggable optical transceivers that operate with four channels in each direction. The original QSFP allowed 4x4Gb/s but three new formats exist, QSFP+ that reaches 4x10Gb/s, QSFP14 reaching 4x14 Gb/s and QSFP28 with a maximum of 4x28 Gb/s. Figure 2.6 shows a 3D model of a QSFP transceiver.

Figure 2.6: QSFP module rendering[15].

Gigabit Interface Converter (GBIC)):This transceiver offers a hot-swappable electrical interface that supports a large number of different physical technologies like copper and optical fibers. SFP transcivers were a variation of GBIC that allowed the same functions but with a higher density and, as so, were initially called Mini-GBIC. In figure 2.7 one can se several GBIC transceivers.

Figure 2.7: GBIC modules[16].

X2/XENPAK: Standardized form-factors for 10Gb/s used in data optical links only. Both transceivers have the same standard electrical interface called XAUI (4 x 3.125 Gbps ). X2 transceivers, presented in figure 2.8, are a smaller and enhanced version of XENPAK and have four versions: SX, LX, EX and ZX. SX are used in multi-mode fibers and the rest are used in single mode fibers, varying the maximum range of 10 km, 40 km and 80 km respectively.

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Figure 2.8: X2 module[17].

CXP: Designed to use in data centers and high performance computer applications. CXP transceivers have twelve channels in each direction with 1Gb/s up to 10Gb/s allowing a rate of 120Gb/s. A CXP transceiver is shown in figure 2.9.

Figure 2.9: CXP form-factor module[18].

SFF: Is used in both in telecommunications and data communication applications. SFF modules exist with a variety of different transmitters and receivers allowing the user to select the appropriate one for the physical technology employed. Maximum data rate is 4.25Gb/s. Figure 2.10 shows a SFF transceiver.

Figure 2.10: SFF module[19].

300-PIN: The 300-PIN MSA schematic is shown in figure 2.11. It has an electrical interface through a 300 pin connector and a optical interface to the fiber. The transceivers are available in 10 Gb/s and 40 Gb/s modules and are mainly used in telecommunications services.

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Figure 2.11: 40 Gb/s 300-pin module schematic[20].

2.2.5 Modules for future optical networks

Future access network technologies demand a high transmission rate to face consumer de-mands.

The limitations imposed by the NG-PON2 standard make SFP+ and XFP modules the perfect candidates to operate as solutions for NG-PON2. In modern PONs, due to the small scale of SFP+ modules, they are preferred as ONU transceivers, as ONU modules need to be cheap because they are deployed in large numbers. Optical Line Terminal (OLT) units can afford to be a little pricier and therefore XFP modules are preferred in OLTs because the slightly larger size allows for more complexity in the transceiver.

In NG-PON2 the complexity of a ONU is very large as the unit requires colorless operation in both the transmission and the reception. This leads to the necessity of more circuitry in the transceivers, which in turn leads to the need for more space, opening up the room for XFP transceivers to shine as a solution due to their larger size.

It is important to note that several of the transceiver modules presented were made with point telecommunication systems in mind, whereas access networks have point-to-multipoint connections.

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2.3 Fiber connectors

Unlike in the electrical domain, where it is only necessary to assure physical contact between the metals of the connectors, optical fibers require a precise fit in order to align. Optical fiber connectors have a structure dedicated to holding the fiber strand in place, called a ferrule, which are made from metal, plastic or ceramic materials.

Simplex fiber terminations have only one connector, while duplex fiber terminations have two connectors of the same type.

There are several types of connectors, with different advantages and disadvantages, and different applications in which they are used. In this report, only the most used connectors will be presented in detail.

2.3.1 Straight tip

Straight Tip Connector (ST) were developed by AT&T and were one of the first widely distributed connector, mainly in Datacom links. As such, ST connectors are the most used, but their relative large size makes them disadvantageous for future technologies.

ST connectors have a bayonet type coupling and a 2.5mm ferrule diameter. A ST connector is show in figure 2.12.

Figure 2.12: ST type connector[21].

2.3.2 Subscriber

Subscriber Connectors (SC) were developed by a Japanese telecommunications company (NTT). This type of connector is also massively deployed in Datacom and Telecom links.

The connector is square shaped, has a snap-in type coupling and has a 2.5mm ferrule diameter. Several SC type connectors are show in Figure 2.13.

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Figure 2.13: SC type family connectors[22].

2.3.3 Lucent

Lucent Connectors (LC) were developed by Lucent Technologies. This type of connector is deployed in high-density connections, like the ones present in transceiver modules.

The connector has the same square shape as the SC one, but has a smaller form factor with only 1.25mm ferrule diameter. It has a snap-in type coupling. Figure 2.14 shows a connector with duplex LC interface.

Figure 2.14: LC type duplex connector[23].

2.3.4 Mechanical Transfer Registered Jack

Mechanical Transfer Registered Jack (MTRJ) are popular small form factor connectors deployed for duplex multimode connections.

They are shaped like a smaller RJ connector always come in a duplex configuration. The coupling is made via snap-in and the ferrule has 2.45mm of diameter. Figure 2.15 shows two MTRJ type connectors.

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Figure 2.15: MTRJ type connector[24].

2.3.5 Ferrule

Ferrule Connector (FC) were developed to use in unstable environments, as screw type coupling makes it very hard for there to be problems in the connection. They are manly deployed in single mode optical fibers in Datacom and Telecom applications. The ferrule diameter is 2.5mm, so they can be adapted to a SC or ST connection. Figure 2.16 shows a pair of FC connectors.

Figure 2.16: FC type connector[25].

2.3.6 Connectors for future optical networks

Transceiver modules are deployed in mass to tackle the large data-rates required in the transmission and reception of access networks.

As these rates increase in response to an increasing consumer demand, the use of smaller and more compact modules become essential to save shelf-space and power consumption. It is then noticeable the advantages of using LC and SC type connectors in these network modules as they have the smaller package and will save considerable space.

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2.4 Measurements and merit figures in NG-PON2

In order to test a transceiver for characterization in NG-PON2, several merit figures need to be checked. The process is different for a ONU transceiver and a OLT transceiver. In chapter 6, a ONU transceiver will be fully characterized so all explanations of measurements and merit figures will be targeted to ONU components.

The most important merit figures, which are absolutely necessary for ONUs in this ar-chitecture, are tunability between four downstream and four upstream channels, burst mode operation, and Bit Error Ratio (BER) measurements.

2.4.1 Channel tunability

NG-PON2 allows four channel operation, with the standard allowing 8 channel operation as well[26], that need to be tunable. For there to be tunability, the transceiver must be able to change the laser parameters to allow the wavelength of the spectrum to change to another channel. Table 2.1 shows the wavelength channels for 4 channel NG-PON2.

Channel Upstream Wavelength (nm) Downstream Wavelength (nm)

1 1532.68 1596.34

2 1533.47 1597.19

3 1534.25 1598.04

4 1535.04 1598.89

Table 2.1: NG-PON2 upstream and downstream channels.

To achieve multi-wavelength networks it is necessary to employ a different laser locked to a specific wavelength in each ONU. However, this greatly increases the burden of network op-eration and maintenance.[27] It is then necessary for a ONU transceiver to be able to tune its reception to one of the downstream wavelengths at will, and its transmission to the correspond-ing upstream wavelength.

In order to do so, there needs to be some sort of mechanism in the reception that allows a change in the band that a photodetector receives, that is, that filters the incoming optical signal to the band desired.

In reception tunability, a component much like the example shown on figure 2.17 is often used.

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Figure 2.17: Exemple of a structure transparent to a certain wavelength and reflective to others[28].

The example above has a single cavity and dielectric Bragg reflectors. The refractive in-dices of the optical layers are varied using controlled temperature changes, thereby shifting the transmission wavelength of the filter[28].

Light waves inside the medium interfere with each other either constructively, making the resulting resonant wavelength able to propagate, or destructively, nulling the wavelengths af-fected. The propagation of these waves inside the medium is controlled by the reflections in the Bragg reflectors.

Thermal modulation on the filter is accomplished by heating using thin film resistors placed directly on top of the optical layers. Variations in temperature alter the refractive index of the materials used for the optical filter[28]. With this concept, one can see how it is possible to tune the reception of a transceiver to a specific channel in architectures with more than one wavelength, like NG-PON2. These changes in temperature can also be achieved with a Thermoelectric Cooler (TEC).

In TECs, a voltage is used between a junction of electrical conductors. By the flow of current between junctions, heat is transfered from one to another. TECs then are capable of transferring heat to a conductor to change and maintain a set temperature.

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Figure 2.18: Schematic of generic tunable laser [29].

Figure 2.18 shows a block diagram and a wavelength plot of a generic tunable laser. A way to control selection filters is to tune them by temperature control. In lasers, the temperature controller is often a TEC.

When using a temperature based mode selection filter, if one has a way to change the temperature set by a TEC on the filter, it is possible then to change the mode of the output optical signal, and therefore its wavelength.

When tuning wavelength channels, one thing of great importance in NG-PON2 is the tuning time between channels. Three classes have been defined for NG-PON2 tuning times[30]. Table 2.2 shows the tunning time classes for NG-PON2.

Classes Tuning time

1 <10 µs

2 10 to 25 ms

3 <1 s

Table 2.2: NG-PON2 tuning time classes.

2.4.2 Laser driving

Driving circuits are relatively simple for Light Emitting Diode (LED) transmitters but be-come increasingly complicated for high-bit-rate optical transmitters employing semiconductor lasers as an optical source[31].

In semiconductor lasers, there needs to be a driving circuit to provide an electrical signal that keeps the laser in threshold, called a bias current, and another electrical signal to modulate the laser.

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Figure 2.19 shows an example of a simple driving circuit based on feedback by a photodiode.

Figure 2.19: Simple driving circuit[31].

An increase in the bias and modulation currents of a laser will increase its output power, which can contribute to an improvement in performance. In NG-PON2 the output power of a upstream signal should be kept between 4 and 9 dbm[7], therefore in a laser of a ONU for NG-PON2, the driving currents must be so that a acceptable value is achieved.

Figure 2.20: Variation of bias and modulation to compensate a change in temperature[32].

Figure 2.20 shows how the bias and modulation in a driving circuit must change to compen-sate the change in the optical output power curve of the laser. But for a constant temperature, the curve stays the same, meaning that if the bias current were to change the Extinction Ra-tio (ER) would decrease as the power of the zero would increase, and ER is given by:

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ER (dB) = 10log(P 1

P 0) (2.1)

If the ratio between the power of the 1 and the power of the 0 stay the same, so does the ER. Changes in the driving currents can change this ratio and, therefore, the ER.

In NG-PON2, the minimum defined ER of a upstream optical signal is 6 dB with the possibility of being lower if the transmitting power is high[7], meaning that a ONU laser in NG-PON2 must have driving currents that allow this value.

2.4.3 Burst mode operation

TWDM-PON used by NG-PON2 requires a ONU to transmit upstream data via burst mode. In burst mode, the ONU is transmitting for a very short amount of time, before its time runs out and a new ONU starts transmitting. When a ONU is not transmitting, its laser is turned off. Due to this, the temperature of the laser drifts during burst mode operation, as it gets hotter when transmitting and cooler when turned off.

Burst mode compensation is the introduction into the driving circuitry of a compensation method that kicks in whenever the laser is turned off to compensate the cooling. That way even when the laser turns off, it will still be kept at the same temperature, and therefore wavelength, it was when transmitting.

Burst mode compensation is especialy important in NG-PON2 compared to other tech-nologies that use Time Domain Multiplexed (TDM) due to the small comparative width of its channels.

2.4.4 BER figures of merit

BER can be defined as:

BER = Bits with errors

T otal number of bits (2.2)

BER measurements are a very straight-forward way to analyze the practical performance of a communication system. BER performance indicates that the system is introducing a lot of errors, and if communication may be difficult, or even impossible. Because of this, BER measurements often make or break a lot telecommunication systems.

In NG-PON2 the merit figure for BER is that the sensitivity, that is the power at which the BER = 1 ∗ 10−3 must be equal or lower than -28 dBm for upstream and -26 dBm for downstream[7]. An additional requirement is that power penalty of the 20 km of fiber, that is

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the difference between sensitivity with and without fiber and called optical path penalty, must be lower than 2 dB for downstream and 0.5 dB for upstream[7].

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Chapter 3

Testing board for next generation

transceivers

The development of new technologies for optical transceivers is at the front-line for devel-opment of next generation passive optical networks. These transceivers are required to perform in line with technological standards whether it is on data rate, optical power or other desired criteria. Test boards must then be designed with testing these criteria in mind and are crit-ical to the development stage of a technology, as they provide the necessary feedback on the performance quality.

One type of transceiver seeing improvements in development to target NG-PON2 is the XFP transceiver. XFP are capable of 10 Gb/s transmission and reception and offer a compact form factor to save on hardware footprint. Development and testing of next generation targeted XFP transceivers would require testing boards designed to operate with the XFP pinout and provide low losses on 10 Gb/s signals inside the board.

This chapter presents the steps taken to design and begin production a board that targets this problem, with the added challenge that the final solution must be as cheap as possible, with price being often used as a deciding factor in design choices. The board functionality is explained, and detailed information is given on its electrical schematic on section 3.1, high-speed line impedance matching on section 3.2, and PCB layout design in section 3.3. The final assembled board is shown on section 3.4 and tested on section 3.5.

3.1 Board Schematic Design

In this section the Schematic design of the board is presented. First, a simple block diagram is shown and each block has its function explained. Afterwards, in the design choices section, some parts of the block diagram are explained in more detail as to illustrate the reason for their design. Lastly, the full electrical Schematic is presented block by block.

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3.1.1 Block Diagram

The block diagram for the board is as presented in figure 3.1:

Figure 3.1: Project Block Diagram.

The XFP connector is at the core of the design and is assembled with a cage to help with heat dispersion. The differential transmitting and receiving electrical signals are sent to SubMiniature version A (SMA) plugs to provide easy connections and access these signals. A fifth SMA plug, for the burst enable signal, is also available. The board also has installed an independent circuit capable of generating the burst enable signal with configurable parameters. A jumper allows users to choose between the SMA and the internal circuit.

The external interface is a typical Universal Serial Bus (USB)-B plug but the XFP is only programed via Inter-Integrated Circuit (I2C) communications, so an internal circuit is present to convert between the two technologies. Circuits capable of reseting the board are present, and LED circuits are installed on all voltage levels and meaningful outputs. A large power source block feeds on a +12 V plug and provides +5 V, -5 V and +3.3 V to the board.

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3.1.2 Design Choices

USB-B:

USB cables are widely used as peripheral connectors. The original USB standard, USB-A, was developed with the intention of being present at the main computing side, not the peripheral side. As such, USB cables to peripheral devices often have two different connectors, with peripheral devices often having USB-B end of the connector.

Three USB-B connectors are generally available: Standard, Mini and Micro. Mini and Macro versions are available to PCB installation with surface pads while the Standard connector is available with though pin installation. Due to design size constrains on the circuit that converts USB to I2C, the though pin installation of the pin interface of the standard connector was preferred and chosen to be in the final design.

Burst-Enable/PWM Circuit:

On a first schematic, the Burst Enable (BEN) signal was only available via the SMA plug but, to increase the variety of tests the board is capable of, a circuit was designed which can produce a Pulse Width Modulation (PWM) signal with user controlled duty-cycle and frequency, emulating burst mode control.

XFP Cage:

The XFP connection could be made using only a connector but, due to the temperature stability reliance of the device, the XFP enclosure is added.

A XFP enclosure, also called cage, is a metallic component design to allow a very large and fast dissipation of heat via the contact surface. The use of a cage in the design will allow larger stability of the XFP results over time with the sacrifice of board size a and a noticeable cost increase.

3.1.3 Detailed Schematic - Power Sources

The circuit of the power block is figures 3.2 and 3.3. In figure 3.2, a +12 V signal is received via a plug, on the lower left. After filtering and rectification, the signal reaches a global symbol which will represent +12 V positive on all the schematics.

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Figure 3.2: Schematic for the positive voltage sources.

On the upper side of the schematic, there are 2 very similar circuits. These circuits are step-down buck converter circuits intended to generate a lower voltage from the input from the global +12 V signal input. Both circuits are tuned to produce different voltages. The upper one generates +3.3 V and the lower one +5 V.

In both circuits, by setting a resistor divider from the output to the VFB pin, the output voltage will be given by:

Vout= 0.765 ∗ (1 + R1

R2) (3.1)

Where R1 is the upper resistor in the divider, and R2 is the lower resistor in the divider. In order to have an output of +3.3 V, R1 = 73.2 kΩ and R1 = 22.1 kΩ. These correspond to resistors R18 and R19 of the schematic. For an output of +5 V, R1 = 133.1 kΩ and R1 = 24.1 kΩ, corresponding to resistors R7 and R6 of the schematic.

The output filter must also be dimensioned to provide good performance of the power source. Table 3.1 is a compilation of information from Texas Instruments for typical values of the feedback resistors and the capacitor-inductor pair for the LC filter used. With this information, inductors L1 and L5 and capacitors C41 and C19 of the schematic were chosen, finishing the design of the positive power sources.

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Output Voltage R1 (kΩ) R2 (kΩ) C(pF) L(µH) 1 6.81 22.1 1.5 1.05 8.25 22.1 1.5 1.2 12.7 22.1 1.5 1.8 30.1 22.1 5-22 2.2 2.5 49.9 22.1 5-22 2.2 3.3 73.2 22.1 5-22 2.2 5 124 22.1 5-22 3.3 6.5 165 22.1 5-22 3.3

Table 3.1: Texas Instruments recomended values for the feedback resistors and output filter for the TPS54327 IC.

On figure 3.3, the circuit used to produce -5 V is shown. The circuit is composed of two equal MAX1853 integrated circuits from MAXIM that invert the input voltage (+5 V).

Figure 3.3: Schematic for the negative power sources.

This circuit has a very simple operation principal. An input voltage arrives to the Integrated circuit (IC) via a input capacitor and is inverted in the output pin and directed to the output capacitor. The input, output and flying capacitors used were presented on a typical voltage inverter circuit by the manufacturer. Because this is a charge-pump circuit, the output current

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is low.

As per indication of the XFP manufacturer, PICadvanced, this circuit must be able to provide more than 30mA, which is the maximum output current of the MAX1853, and therefore two circuits used in parallel would be needed. As the MAX1853 was already in stock, this solution was preferred over choosing another IC, with higher output current, to minimize costs.

3.1.4 Detailed Schematic - USB to I2_C

The circuit of the USB to I2C block is presented on figure 3.4.

Figure 3.4: Schematic for USB converting circuit.

Focusing on the lower left corner, the USB connector is directly connected to a diode array integrated circuit, meant to protect the circuit from overvoltage. The USB Bus and differential signal is then sent to the main chip. The rest of the main chip consists of the power ports, i/o ports and not connected ports.

Three ports, configured as open-drain, have a pullup resistor to the +3.3 V supply to pull the lines. Two of these lines are the I2C Data line, SDA, and I2C Clock line, SCL.

The Reset port is connected to a not mounted capacitor to allow a physical short of the line to provoke the reset. The outputs of the block are the I2_{C lines which will connect to the XFP} and provide interaction with it via USB.

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3.1.5 Detailed Schematic - PWM circuit

The PWM circuit is responsible for generating a squared signal with variable frequency and duty-cycle in order to control the burst enable signal of the board.

The PWM circuit as designed in SPICE is presented below in figure 3.5:

Figure 3.5: PWM circuit design in SPICE.

Two transistors, on the upper left conner, are in a current mirror assembly that mirrors the current flowing in resistor R14 to collector of transistor Q4. As this node is connected to two opamp inputs and a capacitor, all current flows to the capacitor.

The voltage on capacitor C4 is rising with the input current and is sampled in the negative input of opamp U7. As this opamp is rail-to-rail, the output becomes the bias voltage of +3.3 V, which is then passed on to the resistor divider of R15 and R16 that assures two thirds of this value in the positive input of the opamp. This behavior makes the opamp output 3.3 V while the voltage in capacitor C4 is less than 2.2 V, and output of 0 V while the voltage in capacitor C4 is more than 2.2V.

After capacitor C4 rises past 2.2 V and opamp U7 makes its output 0 V, the gate of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) M3 has the same voltage as the source, which is ground, causing the MOSFET to be off. This then cuts the connection between the drain and source, and therefore the ground, making resistor R18 connect to the gate of MOSFET M2, which was until now off. By raising the voltage in the gate of MOSFET M2, a connection is made between the source and drain, making the voltage at the drain 0 V. As the drain of MOSFET M2 is the same node as capacitor C4, the voltage in capacitor C4 becomes 0 V as well. This, in practice, creates a triangular wave at C4 that rises almost linearly until 2.2 V,

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then goes back to 0V in an instant and repeats.

The triangular wave voltage at C4 is forwarded to opamp U8, which is a rail-to-rail opamp with a constant voltage at the positive input. When the triangular wave is bigger than the constant voltage, the output of the opamp is 0 V, and when it is smaller the output is 3.3 V. As so has a square wave is achieved in the output.

To control the duty-cycle of the output square wave, one simply has to control the constant voltage at the positive input of opamp U8. This is done by having a resistor divider with a potentiometer. In the final solution the resistor divider used is shown below in figure 3.6.

Figure 3.6: Duty cycle resistor divider.

The constant voltage will be taken from the central pin of the 5 kΩ potentiometer. When the potentiometer is all the way to one side, resistor R3V is the top resistor of the divider and the bottom resistor is P plus resistor R0V. When the potentiomenter is to the other side, the top resistor of the divider is R3V plus P and the bottom one is R0V. With the values shown and the voltage in the divider given by the equation 3.2 below, the range becomes [0.04 , 2.05] V.

Vout=

Rbottom

Rbottom + Rtop ∗ 3.3 (3.2)

Since the triangular wave reaches 2.2 V, with this range the duty cycle will be variable between 1.8% and 93%.

The last remaining feature is to control the frequency of the output wave. This is done by increasing or decreasing the rising time of capacitor C4. The following equations show how to control the frequency of the output wave:

IR14 = 3.3 − VBE R14 (3.3) IR14= IC4= C ∗ dV dT (3.4)

Since the voltage is variable between 0 and 2.2 V:

F requency = 3.3 − VBE

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Since the target central frequency is 8 kHz, with a capacitor of 10 nF, the resistor R14=16,8 kΩ. To make it variable, this resistor is simply replaced with a 5 kΩ potentiometer and a 15 kΩ resistor. Like this, resistor R14 will always be between 15 kΩ, when the potentiometer is all the way to one side, and 20 kΩ when all the way to the other side. The resulting range, using equation 3.5, is [6.75 , 9] kHz.

Figure 3.7 shows the design in the schematic, now with the numeration used for this board.

Figure 3.7: PWM design in the board schematic.

Figures 3.8 and 3.9 show the circuit simulation in SPICE. In figure 3.8, red is the voltage at the capacitor and green is the voltage at the output of the first opamp. In figure 3.9, red is the voltage at the capacitor and green is the voltage at the output of the circuit.

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Figure 3.9: PWM circuit output simulation.

3.1.6 Detailed Schematic - Main Block

Lastly, figure 3.10 provides a view of the main schematic. This schematic shows the bulk of the electrical circuit and represents all three previous circuits as blocks to make it easier to comprehend the design.

Figure 3.10: Main schematic.

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the XFP, they have the same pinout and as such it is easy to see all connections to the connector in the schematic as direct connections to the XFP pinout. These pinout connections will be now explained.

Starting with the power supply pins shown in table 3.2 Pin Signal

2 -5 V

6 +5 V

8 +3.3 V 9 +3.3 V

Table 3.2: Power supply pinout

Both the +5 V and +3.3 V signals are followed by a filtering stage to guarantee stability in the voltage level. The -5 V signal does not have a filtering stage as complex as the others as it provides considerable less electrical current. In the case of the XFP, filtering stages are required by the MSA. All three of the power supplies are connected to the XFP via a jumper that can be shorted or disconnected at will.

The I2C lines are outputs in the USB to I2C Block and are connected as follows in tabel 3.3.

Pin Signal

10 The clock line (SCL) 11 The data line (SDA)

Table 3.3: I2C pinout

The I2C lines are connected to their respective pins via jumpers that control whether the connection exists or not.

Via the SMA plugs, arriving Tx differential signals and outbound differential Rx signals have the following pinout shown on table 3.4.

Pin Signal 17

Rx-18 Rx+

28

Tx-29 Tx+

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Pin 13 of the XFP can either be an input to disconnect the XFP at HIGH state, on an OLT, or an input to reset the XFP at HIGH state, on a ONU. As such, with the use of a jumper, Pin 13 is connected to ground with the jumper shorted (OLT configuration) or is connected to a pullup resistor at 3.3V with the jumper disconnected (ONU configuration).

Pin 5 of the XFP can either be an input to disable the XFP ate HIGH state, on a OLT, or an input to receive the Burst enable signal, on a ONU. The Burst enable can either be generated from the BEN block or received via a SMA plug. As such, a 3-way jumper and a 2-way jumper are used as presented:

• A 3-way jumper and a 2-way jumper are used.

• When the 3-way jumper is shorted between the first two ports, pin 5 receives a Burst Enable signal from the BEN block regardless of the configuration of the 2-way jumper. (ONU configuration).

• When the 3-way jumper is shorted between the second set of ports, and the 2-way jumper is disconnected, pin 5 receives a Burst Enable signal from the SMA plug. (ONU configu-ration).

• When the 3-way jumper is shorted between the second set of ports, and the 2-way jumper is shorted, pin 5 is directly connected to ground. (OLT configuration).

Several pins have diagnostic LEDs. Pin 14 is the receiver loss of signal output and has a small LED circuit with a Field Effect Transistor and a resistor to allow LED monitorization. Pin 4 is the transmitter signal detected output and has a small LED circuit with a Field Effect Transistor and a resistor to allow LED monitorization. Lastly, all three of the power supply pins have a separate LED control.

The remainder of the pinout is presented on table 3.5:

Pin Signal

1, 7, 5, 12, 16, 19, 21, 23, 26, 27 and 30 Ground

3, 20, 22, 24 and 25 Not connected

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3.2 Impedance Matching for 10 Gb/s Transmission Lines

Impedance matching is fundamental to the design of boards with high-speed lines. In the case of boards to test high speed transceivers, bad impedance matching can result in a loss of several dB, which makes testing unreliable and can rend it impossible. In this section, the high-speed lines will be dimensioned to achieve a good impedance match. At the end of the section, the particular case of the USB lines will also be talked about.

To match a line’s impedance, it’s dimensions must be calculated in accord to the physical characteristics of the board materials.

The first step in dimensioning the lines of a board is to know the board’s stackup. A stackup is the physical composition of the layers. In this design the stackup is as shown in table 3.6:

Layer Type Description Thick.(mil) Thick.(mm) r Diel. Material

Dielectric SolderMask 0.8 0.02

1 Signal MicroStrip 1.4 0.035

Dielectric Core 61 1.55 4.2 FR-4

2 Signal MicroStrip 1.4 0.035

Dielectric SolderMask 0.8 0.02

Table 3.6: Stackup Parameters - XFP two-layer design.

Most of these values were chosen as to make the board as cheap to manufacture as possible, as foundries often offer better prices if the boards are made with a stackup that is similar to other projects they may have in production. The reason behind the choice of a FR-4 board is that the material is very often used and is normally the cheapest option offered, but it is known that FR-4 does not offer a good high frequency response.

3.2.1 Online Impedance Calculator

The first tools used were simple line impedance calculators. Several of these calculators are easily found online. The following figure shows an interface from one of the several impedance calculators found.

All calculators present a series of rules for which the used equations work, in the case shows it is that a ratio between the trace width and dielectric thickness must be between 0.1 and 3. Other calculators presented sometimes two or even three set of rules to be kept. Due to these rules the results are not correct for the desired stackup. In one case, a trace would have to be over 6mm in width to keep with the rules, which is very far off from the acceptable results of between 0.1 mm and 0.4 mm.

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3.2.2 AWR - National Instruments

AWR Design environment offers a free transmission line calculator tool called TX-LINE. TX-LINE is widely used to calculate line impedances and the results can be trusted to be precise. The dielectric constants and loss tangent can be input, as well as the stackup parameters. The remainder of parameters can be changed to find the ideal result. As the high-speed lines are differential, the desired impedance is 100 Ω differential.

The TX-LINE tool can not calculate differential coplanar lines, as such differential coupled lines were calculated instead. The output can only be the even mode impedance or the odd mode impedance. Since the differential impedance is twice the odd mode impedance, the target odd mode impedance is 50 Ω.

Figure 3.11: TX-LINE results.

Using TX-LINE the transmission line solution is presented as being a width of 0.8 mm for a gap of 0.2 mm, as shown in figure 3.11

3.2.3 Saturn PCB

Saturn PCB Design is another free tool that is also used very often in impedance line calculations for PCB design. Unlike TX-LINE, Saturn is not a simple interface program with a very minimalist approach. In fact, Saturn offers tools to a variety of different PCB Design calculations, not only transmission line calculators.

Once again all stackup information is typed in Saturn and the values for width and spacing are manually changed to find the best impedance match. Saturn immediately calculates the differential impedance so the target impedance is 100 Ω.

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Figure 3.12: Saturn PCB design results.

The results obtained with Saturn PCB Design are 1 mm of trace width for 0.2 mm of spacing, as shown in figure 3.12. This is a very large difference from the TX-LINE results.

This result is not good as it is still outside the preferred solution. In fact, a 1 mm trace is a very large trace and will not be used in this design. Saturn is widely used and has very powerful tools, but the model used to represent the stackup is not perfect so the results can be with error. This also applies to TX-LINE, as the model used was the same, and in both cases the coating dielectric layer is not taken into account.

3.2.4 POLAR Instruments - Transmission Line Field Solver

The POLAR tool was the most powerful tool used. Unlike Saturn it is used only for trans-mission lines, but has a very large complexity to the calculations.

POLAR has a very large number of models to choose from and such it was possible to use a model exactly like the one of the stackup.

The procedure is the same. Insert the stackup parameters and then change the width and separation to achieve 100 Ω of impedance. One can notice how using POLAR there are several more stackup parameters to be input that were left out in other software.

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With POLAR, 0.4 mm trace width with 0.25 mm trace separation was achieved, which are in the desired parameter range. Results of this simulations are shown in figure 3.13.

3.2.5 Final Solution

POLAR Instrument’s Transmission Line Field Solver is the most complex tool, as it is the only one which allows full use of the stackup information and produced the best results. The solution obtain in this software will be used to design the high-speed lines in the board.

3.2.6 USB Lines

The USB standard forces the USB lines to have an impedance of 45 Ω each and 90 Ω differential.

Due to the pinout requirements of the chip that converts USB to I2C, the USB lines are limited to 0.3 trace width are forced to not have a similar separation along different parts of the line. The results of the USB line calculations in POLAR are presented below, but due to the mention problems, the line is shown to have about 100 Ω of impedance, which is about a 11% deviation from the target value. Results are shown in figure 3.14.

Figure 3.14: POLAR Instruments results for USB lines.

3.3 Printed Circuit Board Layout

It is of most importance to make the design as cheap to produce as possible. As such, the design was implemented in a 2-layer printed circuit board.

A 2-layer limitation on the board impacts mainly the required size of the board and the design choices required, especially in regards with the power lines, that no longer have a separate plane, as they normally do in 4 or more layer designs. Both layers are composed of connected ground planes covering most of the surface, being interrupted as less as possible to maintain a good behavior of the electrical ground. Interrupted or bottlenecked ground planes often result in small voltage variations along the ground plane, which is very unwanted.

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All components and silkscreen are placed on the top layer. Along the top layer there are also four separate planes for power sources: +12 V, +5 V, -5 V and +3.3 V. All pins connected to the different power supplies are in contact with these planes to allow maximum current circulation. Feeding current to a pin via a line, instead of a plane, limits the maximum current the pin can use before causing electrical issues on the line.

On the top layer, electrical circuits, power plugs and the USB plug are placed on the left side of the board. The XFP connecter and enclosure are placed on the right of the board. All SMA plugs are placed on the top side. As a general rule, all connections are traced on the top layer, but to avoid crossing lines, some lines are traced in the bottom layer, mainly on the right side of the board.

All high-speed lines were designed so that differential lines are close together, as all impedance matching calculations used a uniform differential pair separation to calculate. It is also a good design rule to avoid bends near the pads and to smooth, as much as possible, the transitions between thin lines and thick pads. When ground planes are present in the top layer and in the bottom layer, it is common to use holes connecting both layers, also called vias, to isolate parts of the circuit from outside interference. As such, the whole board was fitted with several vias along the outer edges to remove interference from electronic devices. The high-speed lines were also designed with surrounding vias to prevent undesirable electrical propagation modes. Figure 3.15 shows some of these vias. Represented in the figure is part of the board drill drawing, which is a representation of the position of all drilled holes in the board using letters to represent the drill size.

Figure 3.15: Drill Drawing. Y shapes are vias limiting the high-speed lines. On the right side, there are vias limiting the board’s edge.

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The final Board size was set at 98mm x92.39mm. This was largely due to needing room for the XFP enclosure and enough space to allow all high-speed lines to reach the SMA plugs without the need for sharp turns.

On the appendixes, three different Gerber images are shown. Gerber is the default output of a printed circuit board design, and is used by a foundry to produce the final PCB.

Appendix A shows the various gerber files for the top board, layer 1, Soldermask and Solderpaste, as well as the generated silkscreen Gerber for easier understanding.

Appendix B, the Gerber files for the bottom layer, Layer 2, Soldermask, and Solderpaste are presented, also showing the top layer silkscreen to allow comparisons with the previous annex. Lastly, appendix C shows all layers on top of each other. This view is not as easier to understand, but is nonetheless present to allow a perspective of all layers of the board at the same time.

3.4 Final 2-layer printed circuit board

To further minimize costs, all components on the board will be welded by hand into the board.

At the time this report was written the assembly process was no yet completed. The XFP enclosure and the PWM generating circuit for Burst-Enable are not yet finalized and still need to be worked upon. Figure 3.16 shows a top view of the assembled board.

Figure 3.16: Top view of the PCB. Metallic pads are present in the areas are still not assembled.

All remaining electrical circuits were tested for electrical functionality and, for the moment, exhibit expected behavior, casting good signs for the future board performance. After all circuits

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are assembled, tests need to be made to the high-speed lines to verify its performance at 10 Gb/s.

3.5 High frequency testing

The assembled board was tested under two different setups to obtain the electrical eye diagram for the transmission and reception of 10 Gb/s signals.

The transmission, or Tx, testing setup is shown in figure 3.17:

Figure 3.17: Tx signal testing setup.

An external clock generator tuned to 10 GHz is fed into a pattern generator to provide an electrical differential Tx signal via two RF cables. These cables will connect to the board’s TX+ and TX- SMA plugs that provide an interface to the XFP installed on the board.

With the TX+ and TX- RF signals, the XFP has the required modulation to create its optical TX signal which will be propagated forward in a fiber to an optical to electrical converter. The O/A converter then gives origin to an electrical signal to be visualized on a real-time scope.

The reception, or Rx, testing setup is shown in the figure 3.18:

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A JDSU board is used to create the incoming optical signal. On this setup, a JDSU board uses the signal from an external pattern generator to modulate an optical signal on a OLT.

The optical signal is received by the XFP in the testing board and is forwarded to the board’s RX+ and RX- SMA plugs. The resulting electrical signals are sent through RF cables to a real-time scope where it is possible to see the eye diagram.

The assembled testing board was tested on the transmission setup. Results were taken for a pattern rate of 5 Gb/s, 7 Gb/s and 10 Gb/s and are represented in figure 3.19.

(a) 5 Gb/s pattern. (b) 7 Gb/s pattern.

(c) 10 Gb/s pattern. (d) New 10 Gb/s pattern. Figure 3.19: Eye diagram results for the transmissions tests.

As the results on figure 3.19 show, the assembly process introduced some distortion in the high frequency performance of the board. The assembly was done on two new boards to see if the RF response could be improved with the eye diagram of these new boards being the same and one of them is show in figure 3.19-d).

All three assembled boards were tested on the Rx signal setup with very similar results, shown in the figure 3.20.

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(a) First board Rx signal.

(b) Second board Rx signal. (c) Third board Rx signal. Figure 3.20: Eye diagram results for the reception tests.

A total of three boards were assembled and tested both on the Tx signals and Rx signals. The first assembled board presented bad performance at high frequencies, but the soldering process was redone with increased care in the other boards to eliminate errors, resulting in much better Tx results.

All boards presented very similar results in the Rx setup, with either assembly process not having a clear advantage over another. This leads to believe that the assembly process that caused problems in the Tx tests was just an unfortunate error, as that board’s Rx signals are acceptable. The functionality of the board was proved for high frequencies, required to perform 10 Gb/s, with good results, especially in the Rx signals. As the rest of the boards functions can be probed via the control LEDs, this analysis allows to conclude that the board is successful as a 10 Gb/s XFP testing board.

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Optoelectronic modules for next generation optical networks

Ricardo Jorge

Mendon¸

ca Coelho

M´

odulos ´

otico-eletr´

onicos para redes ´

oticas de

futura gera¸

c˜

ao

Optoelectronic modules for next generation optical

networks

Ricardo Jorge

Mendon¸

ca Coelho

M´

odulos ´

otico-eletr´

onicos para redes ´

oticas de

futura gera¸

c˜

ao

Optoelectronic modules for next generation optical

networks.

Dedico este trabalho aos meus pais e restante fam´ılia

sempre pr´

oxima de mim.

Contents

List of Figures

List of Tables

Acronyms

Chapter 1

Introduction

1.1

Motivation

1.2

Objectives

1.3

Structure

1.4

Contributions

Chapter 2

Transceivers for next generation

optical networks

2.1

40-Gigabit-capable PON (NG-PON2)

2.2

Transceiver modules

2.3

Fiber connectors

2.4

Measurements and merit figures in NG-PON2

Chapter 3

Testing board for next generation

transceivers

3.1

Board Schematic Design

3.2

Impedance Matching for 10 Gb/s Transmission Lines

3.3

Printed Circuit Board Layout

3.4

Final 2-layer printed circuit board

3.5

High frequency testing