C nMOS W (iiia) L (jum) Ida (mA)

Ri (il)

⁶⁰⁰

^Mi

^{16x2.5 0.18 1.67}

C\ (PF)

^16.5

Msw

^{24x2.5 0.18 0.84}

Table 6.2: SBM

design

^values.

6.4.2

LO Phase Shifter

There are several _{ways to}

implement

^{a 90°}

phase

^shifter.

Here,

^before

going

^into the details of the chosen

implementation,

^we

briefly

^discuss

the four

predominant

methods used within

integrated-circuits:

• RC ^— CR Network: A 90°

phase

^{shifter can} be realized with

LOo-

Figure

^{6.7: RC—CR}

phase shifter.

an RC

low-pass

^{and a CR}

high-pass

^{filter as shown in}

Fig.

^6.7.

Provided the resistors and the

capacitors

^are

matched,

^the

phase

difference is

independent

^from

frequency.

^{If the two filters are}

6.4.

Image-Reject

^{Mixer 55}

loaded

by

^matched

loads,

^the

phase

difference results also inde¬

pendent

from the load. On the other

hand,

^the

amplitude

^{is the}

same

only

^{at the -3 dB}

frequency

^{which is set}

by

^{an RC}

product, and,

^due to process

variations,

^{in a worst-casescenario can}vary as much as ±40%. To restore

equal amplitudes limiting ampli¬

fiers

following

^the

phase-shifter

^are needed. To be effective such

limiting amplifiers requires

^a

quite high

power

consumption.

^A further

disadvantage

^{of this} type ^of

phase-shifter

^is the need for

anLO buffer. The

lossy input impedance

of the networkcannot be

directly

^driven

by

^an LC oscillator.

Sequence Asymmetric Polyphase

^{Network: A 90°}

phase

^shifter

which also introduces

only

^small

amplitude

^{errors can be}

imple¬

mented with the

help

^of sequence

asymmetric polyphase

^net¬

works,

often called

polyphase

^{filters. A two} stage

polyphase phase-shifter

^{is shown in}

Fig.

^6.8. The RC time constant of each

LO

Q

Figure

^6.8:

Polyphase phase shifter.

sectiondetermines the

frequency

^{atwhich the}

amplitude

^{and the}

phase

errors are zero.

By cascading

several sectionsa broadband

phase-shifter

^can be realized. Due to the

cyclical

^{connection of}

thecomponents, ^a

polyphase phase-shifter

^isless sensitivetocom¬

ponentmismatch than an RC^—CR one. A

disadvantage

^{of this}

structure is the attenuation introduced

by

the network. A two stage

phase-shifter

which has been

successfully

^{used in a} proto-

56

Chapter

^6.

Design

of the Receiver

type

during

^this

project [\ '»]

^{shows an} attenuation of 3.2 dB and isthus

comparable

^tothe attenuation introduced

by

^anRC—CR

phase-shifter. Also, similarly

^{to an RC —CR}

phase-shifter,

^the

low and

lossy input impedance

of the network dictates theuseof

an LO buffer

amplifier.

•

Coupled

^VCOs: A further method which can be used _{to gener¬}

ate

quadrature

^{/ and}

Q

^LO

signals

^is

by coupling

^two oscillators with the same nominal oscillation

frequency

^as

proposed

ⁱⁿ

[', ].

If the oscillators are

coupled

^too

loosely,

the oscillators do not

synchronize.

^{If the}

coupling

^{is too} strong ^the

phase-noise

^de¬

grades.

Therefore the

quadrature

^oscillator

performs

^as

expected only

^{over a limited} range of the

coupling

coefficient

[

^*

>].

^Since

this solution does not

require

^buffer

amplifiers,

^{it shows a}

slight advantage

^intermsofpower. This

advantage

^ishowever

partially

lost dueto the need fortwo oscillators.

•

Digital

^{Divider: A}

digital divide-by-two frequency

divider consti¬

tuted

by

^two latches clocked on the

opposite edges

of the clock generates^two

signals

^{with a}

phase

difference of 90° whichcanbe used as / and

Q

^LO

signals (Fig.

⁶

9).

This kind of

phase-shifter

C•>

Q

o

r L_{D Q}

D-latch

]CLKQ

D Q

D-latch

]CLKQ

Lo r

r°

(2*fL0)

O-L-

Figure

^6.9:

Digital divide-by-two phase shifter.

is _very wideband

(ideally

^{from DC to an}upper limit determined

by

^the

latches),

verycompact, ^and very

precise.

The main draw¬

back is the need for an oscillator

running

^{at twice the}

required frequency.

^This

disadvantage

^{in a} transceivercan be turned into

an

advantage by considering that,

^{due to} the different

frequen¬

cies,

^no interaction between the output ^{of the} PA and the LO

6.4.

Image-Reject

^{Mixer 57}

signal

^{can occur. At GHz}

frequencies

^the power

consumption

of

frequency

dividers becomes

relatively high, but, considering

the buffers or

limiting amplifiers required by

^other

solutions,

^the

power

consumption penalty

^is not very^severe.

Due toits_many

advantages

^we have decidedto

implement

^a

digital divide-by-two frequency

^divider

phase-shifter.

The main factor

limiting

the achievable

quadrature

accuracy

using

this kind of

phase-shifter

^is

the even-harmonics content of the VCO

signal driving

^the

circuit,

^as even-harmonics cause the

duty cycle

^{of the}

signal

^to deviate from the ideal 50% ^{value. We}

analyze

^the

phase

^error

generated by

the second- harmonic

alone,

^since

higher

even-harmonics are

always significantly

lower than the secondone.

Fig.

^{6.10shows the}

phase-error

^a

generated by

^the

signal

A[sia(ujt)

^A-K

sia(2ujt A-4>)} (6.16) driving

^an ideal master-slave

D-flip-flop

^{as a} function of the relative

amplitude

of the second-harmonic component ^with respect ^{to the fun¬}

damental

K,

^{for three}

phases </>.

^The

phase-error

^{a is}

amplitude

^and

phase dependent:

if the second harmonic component ^is

in-phase

^with

the fundamental

(</>

⁼

0),

^{no error is}

^produced;

the maximum error is caused

by

^a

phase

^difference

</>

^{of 90°. As}

usually

^{it is not}

possible

^to

control the relative

phase </>,

^the

only

^{meantominimizethe}

phase-error

ais to

keep

the second-harmonic and all

higher

even-harmonic_compo¬

nents as low as

possible.

^{For this reason it is} very

important

^{to use a} VCO with a differential

topology.

The

implemented divide-by-two frequency

^divider

(Fig. 6.1])

^has

been

designed

ⁱⁿenhancement source

coupled logic (ESCL)

with resis¬

tive loads. The circuit is

composed by

^a

couple

of latches clocked in

anti-phase. Having

^a

fully

differentialstructure ESCL gates

inject

very little noise into the _power

supply

^{and the}

substrate,

^{and are immune}

to common-mode noise.

Furthermore, working

with low level

signals they

^aremuchmorepowerefficient than other

logic

families. The static power

consumption

^{of this}

logic family

^{is ofno concern} here since the divider is

always working

^{at full}

speed.

The

predominant

^{RC timeconstant}

limiting

^the

speed

of the circuit is constituted

by

the load resistors and the total

capacitance loading

the output ^nodes.

Thus, knowing

^{the load}

capacitance,

^the

required

58

Chapter

^6.

Design

of the Receiver

relative

amplitude

^K

[dB]

Figure

^{6.10: Relative}

phase-error

between the L and

Q signals

^{as a}

function of

the relative

amplitude of

the second-harmonic withrespect

of

the

fundamental

component

of

^the

signal driving

^an ideal master-slave

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