V 0.18 ina

42

Chapter

^5. 0.18 /Lxm CMOS

Technology

Process Substrate Metals

Supply Voltage

l'ox

p-type/Triple

^Well

6

layers

1.8 V

Chapter ⁶

Design ^of the Receiver

6.1 Nonlinear Distortion of MOSFETs

In this

section,

^{weestimatethe}

magnitude

of the intermodulation

prod¬

ucts

generated by

the nonlinear I-V characteristic ofa MOS transistor.

In

particular

^wecalculate the

input

referred third order

intercept point

of a common source

amplifier assuming

that the I-V characteristic of the transistor is the dominant

nonlinearity.

The results areuseful as a

yardstick during

^{the first}

phase

^{of the}

design.

We describe the characteristic of the device as

[10]

Id(vGs)

⁼ oh , fl,

ß

tttt(«gs-

Vp)2 (6.1)

2[1 A-0(vGs ^-

Vt)\

where

ß

^isthe transconductance

factor,

^{and 6 isa}

mobility degradation

factor which for the used_processis around 3

V~1.

Since the intermod¬

ulation

specifications

describe low level

nonlinearities,

^we

expand

^the

above I-V characteristic in a

Taylor

^{series and truncate it after the}

third order component:

dld

Ä 1

d2Id

₂ 1^.3

-r àvas ^A-

t^1Tö-övgs

+ ^7T^Th' dvGS 2! _dv2GS ^L"s 3!

dvGS Id(vGS)

^«

Ido

⁺ _^r—SvGS ⁺ _7-1-^Sv2GS ^{+ -—r-Sv}

=

Id0

A-

a-iSvas

A-

-y5v2GS

⁺

-^Svas ^(6-2)

When two

signals

^of

equal amplitude

^are

applied

^{to the}

input,

^i.e.

Svqs

⁼

A[sm(u>it)

^A-

sm(u>2t)],

the third ordercomponent ^{of the}

Taylor

43

44

Chapter

^6.

Design

of the Receiver

Figure

^6.1:

Input referred

third orderintercept point

of

^{a MOS tran¬}

sistor.

expansion

generates ^the

following

^sidebands:

a3

~3\°Vgs-5v3r ^as

A*

6

'

4

{3sin[(wi -2w2)t]

⁺

3sin[(2wi -w2)t]}

^+...

(6.3)

The third order

intercept point

^{isdefinedasthe}

signal

^levelatwhich

the above sidebands have the same

amplitude

^asthe

input signals

^am¬

plified by

the first order term _a\

Svgs

^{and can} thus be calculated

as:

CL\ A ⁼

=> A ⁼

Hi .A3-

Inserting

the values of_a\ and _as, calculated from

(6

^]

)

^{we obtain:}

A ^— A

V2

2

vod(i

+

evody(2

⁺

evod)

3

1/

⁰

where _vod is the overdrive

voltage

^{defined as}

Vod ⁼

VGso

^-

Vp

(6.4) (6.5)

(6.6)

(6.7)

6.2. Low Noise

Amplifier

⁴⁵

V,nO

Figure

^{6.2: LNA} input stage

configurations.

and

Vgso

is the gate-source ^bias

voltage.

^{We see} that the iIP3 is a

function of_vod. The

higher

the overdrive

voltage,

^the

higher

^{the iIP3}

(Fig. 6.1).

At overdrive

voltages

lower than about 100

mV,

the transis¬

tor enters the moderate inversion part of the I-V characteristic which deviates

substantially

^from

(6.1 ).

At overdrive

voltages

lower than 0 V the transistor is in weak inversion and its characteristic becomes _expo¬

nential

[31].

^{As a}

result,

the iIP3 for _vod ^< 100 mV

degrades rapidly approaching

^{avalue of—}

12.7+201og(n)

^{dBu for}

negative values,

^where

n is the

slope

factor which for the used _process is 1.43.

6.2 Low Noise Amplifier

The characteristics of the LNA to be realized are shown in

Fig.

^4.5.

In

addition,

^to

properly

^{terminate the}

preselection filter,

^{a 50 il}

input impedance

^is

required.

The 12 dB of

gain

^{can be}

implemented

^with

a

single

stage

amplifier, and,

^to avoid the need for a

balun,

^{we use a}

single-ended topology.

For this

design

^{the three}

input

stage

configurations depicted

ⁱⁿ

Fig.

^6.2 have been considered:

configuration (a)

^{makes use of feed¬}

back torealizeabroadband

input matching.

^{Due to}feedback thestage is _very linear and

relatively

insensitive to

parasitics,

^{but to}realize the

required input impedance

^and

gain

^it

requires

^a

large

transconductance and thus a

large

^current.

Configuration (b)

^{is a} common-gate stage.

The

input impedance

^{is defined}

by

the transconductance _gm of the transistor.

By making

gm ⁼ 20 mS a broadband 50 il

input imped-

46

Chapter

^6.

Design

of the Receiver

Figure

^6.3:

Simplified

^schematic

of

^{the LNA.}

ance is realized. The

linearity

^{of the} stage ^is poorer than that of

(a),

but it is still much better than

required

^{for this}

application (Fig.

⁶

1).

The minimum achievable noise

figure

^{is 2.2}

^dB.1 Configuration (c)

^{is a}

common-source stage ^{in which the} gate-source

capacitance Cgs

^{of the}

transistor is embedded in a

matching

^{network to}transform the _capac¬

itive

input impedance

of the transistor to 50 il. For

Q

greater ^than one, the

matching

network formed

by Ls, Lg,

^and

Cgs

^also

^provides

some

voltage gain

between the

input

^{and the} gate-source ^terminals of the transistor so that the effective transconductance of the stage

Gm

⁼

1-o/Vm

^is

larger

than the transconductance _gm of the transis¬

tor.

Therefore,

^toachieve the

specified gain,

^{alower currentis}

required

than with acommon-gate

configuration.

^{On the}

negative side,

^{the volt¬}

age

gain

^{of the}

matching

^network

degrades

somewhat the

linearity

^of

the stage, ^{but not to the}

point

^to

preclude

^{its use for the}

application

at hand. Due to the

tight

^{constraint on} power

consumption

^{we have} decidedto use

configuration (c).

Figure

^{6 3} shows the schematic of the

complete

^LNA

(without

^bi¬

asing)

^{. An}

^analysis

of the circuit withanidealized transistor model in¬

cluding only

the transconductance _gm and the gate-source

capacitance Cgs ^provides

^the

following design equations

^{for the}

input impedance Zm,

^the

voltage gain Av,

and the noise factor

Fld

calculated consider-

1Assuming 7⁼2/3

6.2. Low Noise

Amplifier

⁴⁷

ing only

the drain noise current source of M

Zin

⁼

ju(La

⁺

Lg)

⁺

-^-

^A-

^ ^(6.8)

Av ^— Gm Zip

=

-JQ

9m

ZL Zp

JUqLs (6.9)

Fid

⁼

l+7n2

p

(6.10)

Here

Rs

^{is the source resistance and}

Zp

^is the total load

impedance

which is the

parallel

^{connection of}

Rd, Ld,

^theoutput

impedance

^{of the}

cascodestage, ^{and the}

capacitive

^load

Cp provided by

the mixer driven

by

^theLNA. The inductor

Ld

isused to tune-out

Cp

^{and the}

parasitic

drain-bulk

capacitance

^of

M2

sothat for the

design only

^{the real} part of the load

impedance

^{has to} be considered. Resistor

Rd

^{is used to} lower the

quality

^factor

Qp

of the load resonator and to

precisely

^set

the

gain

^{of the}

amplifier.

Cascode transistor

M2

^{is usedto}

improve

^the

unilaterality

^{of the}

amplifier.

One of the functions of the

amplifier

^{is in}

fact to minimize the emission of

spurious signals coming

from the LO

through

^{the mixer.}

From

(6.9)

^and

(6.10)

^{it is} evident that a

high Q simultaneously

reduces the noise factor and the

required

gm. On the other

hand,

^a

high Q

also reduces the bandwidth of the

matching network, and,

^{if madetoo}

high,

calibration becomes_necessary. As the

matching

network hastobe

integrated along

^{with the}

amplifier,

^{tolimit the}

impact

^ofcomponent

tolerances,

^the

quality

^factor

Q

^{hastobe limitedto}values in the_range of 2-3. From

(6.9)

^{it is also} apparent that the transconductance of the

input

stage

Gm

^{is set}

by Ls.

A

high Gm requires

^{a small}

Ls

whichcan

readily

be realized withashort

bonding

^wire.

Lg

^and

^Ld

^are

implemented

^as

on-chip spiral

inductors. The values of thecomponents used to

implement

^our prototype ^arelisted in Table 6.1.

The current

required by

^the

amplifier

^{is 1.2 mA and is set}

by

^lin¬

earity requirements.

^Transistor

M\

is in fact biased at the

boundary

48

Chapter

^6.

Design

of the Receiver

it, _L,

^G

MUM2

Lg

^{7.5 nH W} 104x2.5 iiia

Ld

^{6.1 nH L} 0.18 iiia

Ls

^{1.8 nH} 9m 18 mS

Rd

^{250 il}

h

^{1.2 mA}

cc

3.7

pF

Table 6.1: LNA

Design

^Values.

between strong and moderate inversion

(Vgs ^—Vp

^{« 80}

mV).

^{A fur¬}

ther reduction of thecurrent

(without

^a

change

in transistor

geometry)

would have made the

linearity

^{of the}system

dependent

uponmoderate inversion characteristics which are not well modeled and thus difficult to

predict

^{and to control.} A simultaneous reduction of current and transistor width in such a way ^as to

keep

the transistor in strong ^in¬

version would have

required impractical

inductor values for the

input

matching

^network.

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