ISSN 2277-1956/V1N3-971-976
Implementation and Analysis of Interval
SRT Radix-2 Division Algorithm
Milind R. Patel 1, Dr. Tejas V. Shah 2, Prof. Deepali H. Shah 3,
1,3Instrumentation and Control Engineering Department,
L. D. College of Engineering, Gujarat Technological University, Ahmedabad-380015, Gujarat, India.
1[email protected] 3[email protected]
2Instrumentation and Control Engineering Department,
S. S. College of Engineering, Gujarat Technological University, Bhavnagar-364060, Gujarat, India.
Abstract− Interval arithmetic gives computation for closed bound set of real numbers which provides two values for single result. It gives confirmation that the error which exists due to the mathematical computation does not exceed over defined accuracy. Interval arithmetic provides higher precision and accuracy than the floating point arithmetic. Software computation for interval arithmetic is quite slow. Hardware implementation of the interval arithmetic provides considerable improvement in speed with respect to its software approach. We have used floating point hardware for interval arithmetic to improve the speed of computation. We present the implementation and analysis of interval radix-2 SRT division algorithm in double precision. SRT division gives faster response when partial remainder is relatively small in computation.
Keywords−Interval arithmetic, Radix SRT division, Floating point arithmetic.
I. INTRODUCTION
In the words of Ramon E. Moore, “If we have, in addition to the results of a computation, error bounds for the differences between the results and the exact solution values, then no matter how these error values were obtained, by analytical means or by further machine computations during or after the given computation, it will always be the case that we have, in effect, for each exact result sought, a pair of numbers: an approximate value and an error bound, or an upper and a lower bound to the exact result”[10].
An interval is closed bound set of real number like [a, b], where a and b are real numbers. Interval arithmetic is simplest way to calculate upper and lower endpoints for the range of values of a function in one or more variables. These barriers are not necessarily the supremum or infimum, since the precise calculation of those values are often too difficult [8]. The width of the interval (i.e., the distance between the interval endpoints) gives an indication of the accuracy of the result. This is useful for monitoring calculation errors such as round off error as well as the effects of approximation errors and errors due to non-exact inputs [8].
The domains of applications of interval arithmetic are wide and varied, ranging from data processing and integrating measurement errors, to geometric representation of solids and computer graphics, constrained global optimization, reliable computing including integration, , monitoring round off error propagation with a strong emphasis on linear algebra [6].
ISSN 2277-1956/V1N3-971-976 II. COMBINED INTERVAL AND FLOATING POINT DIVIDER UNIT
For the values of X = [xl, xu] and Y= [yl , yu] interval divider can be computed as [4]:
Z = X ÷ Y = [min( ∇(x
l÷yl), ∇(x
l÷yu), ∇(x
l÷yl), ∇(x
l÷yu )), max (∆(x
u÷yl),∆(xu÷yu),∆(xu÷yl),∆(xu÷yu))]
Where ∇ denotes rounding downward toward negative infinity and ∆ denotes rounding upward toward positive infinity.
Figure 1 shows a block diagram of the combined interval and floating point divider unit. Compared to the floating point divider, the combined unit requires two additional input registers and one additional output register [4]. It also requires multiplexers to select the interval endpoints, and control logic to set the rounding mode appropriately. By setting certain control bits, this unit is capable of performing either interval or floating-point division. In interval arithmetic, there are seven different cases for interval division computation [4].
Figure 1 Combined Interval and floating-point Divider Unit
In figure 1 two multiplexers select the endpoints to be divided based on the toggle bits, tx and ty. If the toggle bit
is one, the lower interval endpoint is selected; otherwise the upper interval endpoint is selected. The values for the toggle bits are determined based on the sign bits of the interval endpoints, sxl, sxu, syl and syu. A control bit le is set to one when the lower interval endpoint is being computed and zero when the upper interval endpoint is being computed [4]. Seven different cases are selected on the basis of sign bits of input interval endpoints.
III. SRT DIVISION ALGORITHM
ISSN 2277-1956/V1N3-971-976 Figure .2 P-D plot of Radix-2 SRT Algorithm
The following recurrence is used in every iteration of the SRT algorithm [7]: rPo = dividend (1)
Pj+1=rPj− qj+1* divisor (2)
Where Pj is the partial remainder at iteration j. In each iteration, one digit of the quotient is determined by the
quotient-digit selection function:
qj+1=SEL(rPj, divisor) (3)
The final quotient after k iteration is then
q= qjr-j (4)
IV. SIMULATION RESULTS AND COMPARISON
Two simulation results of floating point Radix-2 SRT division and Interval Radix-2 SRT algorithms described. Comparison between these two algorithms on the basis of time, clock report and area are shown in this section. These modules are programmed into Verilog HDL language, implemented by Xilinx ISE 13.2 synthesis tools and simulated using Modelsim 10.0b SE tools.
ISSN 2277-1956/V1N3-971-976 A. Floating point radix-2 SRT division algorithm
In SRT-2 division, the quotient digit is set to one if the partial remainder, 2P, exceeds or equals to the value of 1/2. Then the next partial remainder is calculated using Pi+1 = 2Pi – q*D. The quotient digit is set to negative one if
the partial remainder, 2Pi, is less than or equal to -1/2 and Pi+1 = 2Pi + q*D is used to calculate the partial remainder
for the next iteration. Otherwise, the quotient digit is 0 and the partial remainder is doubled. In the top module of this algorithm first partial remainder logic is designed and then on the basis of hidden sign bit in partial remainder logic the quotient digit selection module is designed.
B. Interval radix-2 SRT division algorithm
It is a combined module of case selection and floating point SRT-2 division algorithm. As per the figure 1 from the four binary data, two data are selected on the basis of toggle bit, tx and ty. These data are converted into floating
point format. After that sign bit is selected using XOR logic, exponents are subtracted and unsigned division is performed for mantissas. Mantissas are divided by SRT-2 algorithm. Figure 4 shows the simulation result of Interval Radix-2 SRT algorithm.
Figure 4 Simulation result of Interval Radix-2 SRT Division Algorithm
C. Comparison between division algorithms
1) Clock report:
ISSN 2277-1956/V1N3-971-976 Table 1
CLOCK REPORT FOR THE BOTH ALGORITHMS
Fan-out Net Skew(ns)
Max Delay(ns) Floating point
SRT-2 division
clk1 340 0.232 1.690
Interval SRT-2 division
iclk1 347 0.228 1.686
le 230 0.227 1.736
2) Timing summary:
From the timing report of both algorithms, floating point algorithm has a lesser frequency and total CPU time than the interval algorithm but the input arrival time and total delay of floating point is increase. Table 2 shows the time report for the algorithms.
Table 2
TIMING REPORT FOR THE BOTH ALGORITHMS
Floating point SRT-2 division
Interval SRT-2 division
Maximum frequency 70.227 MHz 74.304 MHz Minimum input arrival time 11.848 ns 11.042ns Maximum output required time 5.531 ns 5.531 ns Minimum period 14.239 ns 13.458 ns Total CPU time 9.59 sec 11.35 sec
3) Area Requirement:
Table 3 shows the area requirement of both algorithms in Automotive Spartan 3A DSP kit. Interval algorithms has lager area due to the two extra register at input side and one extra register at output side than floating point algorithm. Numbers of bonded input/output are almost double in interval algorithms and also there is one extra global clock.
Table 3
AREA REQUIREMENT FOR THE BOTH ALGORITHMS
Floating point SRT-2 division
Interval SRT-2 division
Total device area
Number of Slices 504 506 16640
Number of Slice Flip Flops
605 629 33280
Number of 4 input LUTs 755 777 33280 Number of bonded IOBs 258 491 519
ISSN 2277-1956/V1N3-971-976
V. CONCLUSION
Interval arithmetic bounds the round off error, truncation error generated due to the numerical computation. It provides two values for single results. An interval’s width indicates the accuracy of results. Software implementation of interval arithmetic is quite slow, so the algorithms programming are performed in verilog hardware description language due to the requirement of hardware support for the faster response. From the comparison of the algorithms total CPU time is more and area is larger in the interval algorithm but provides higher precision and accuracy than the floating point algorithm.
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[11]Kihwan Jun
