Process and Temperature Compensation of CMOS Ring Oscillators

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F

ACULDADE DE

E

NGENHARIA DA

U

NIVERSIDADE DO

P

ORTO

Process and Temperature

Compensation of CMOS

Ring Oscillators

Henrique Manuel Dias Cavadas

MESTRADOINTEGRADO EMENGENHARIA ELETROTÉCNICA E DE COMPUTADORES

Supervisor: Prof. Cândido Duarte (FEUP) Co-Supervisor: Miguel Pina (SiliconGate)

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Abstract

Nowadays, almost any integrated circuit (IC) requires a stable clock signal due to the increase integration of digital systems. To minimize the cost, some applications which require lesser ac-curate clock generation (but still stable) do not use external crystal reference. Ideally, the clock generator block should exhibit a reasonably low frequency deviation when subject to process, volt-age, and temperature (PVT) variations, such as changes in temperature caused by heat generated by the device or environmental changes. Changes of process are, in contrast, static and permanent for each device, as they occur due to parameter deviations during the fabrication process and are usually compensated by trimming. Several CMOS effects have been studied such as threshold voltage (VT) and zero temperature coefficient (ZTC).

The use of simple oscillator topologies so that they can be fully integrated on-chip is possible, but does not provide any compensation in regards to PVT changes. As such, to realize a more reliable oscillator, a compensation scheme must be integrated so that the oscillation frequency can be stabilized.

The main objective of this work is the CMOS circuit implementation of a PVT insensitive oscillator suitable for full on-chip integration. A single ended current starved ring oscillator topol-ogy was analysed taking into consideration PVT behaviour and frequency variation to control and supply voltage deviations. Several techniques are explained which helped to obtain, organize and classify data in a efficient and scalable manner. A topology was developed for matching two sets of lines with similar features on different circuits, containing gain, offset and coefficient of temperature.

Finally, a complete implementation of a fully integrated PVT compensated oscillator is pre-sented with a maximum error of 1.72%. It comprises a single ended current starved ring oscillator, a VTextractor for process and temperature compensation as well as two on-chip voltage references.

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Resumo

Actualmente, quase qualquer circuito integrado (IC) necessita de um sinal de relógio estável devido ao aumento da integração de sistemas digitais. Para diminuir o custo, algumas aplicações que necessitam de um sinal de relógio menos preciso (mas ainda estável) não utilizam cristais de referência externos. Idealmente, o bloco de geração de relógio deve exibir um desvio razoavel-mente baixo de frequência quando sujeito a variações de processo, tensão e temperatura (PVT), tais como alterações na temperatura causadas pelo calor gerado pelo dispositivo ou alterações ambientais. Alterações no desvio do processo de fabrico são, em contraste, estáticas e perma-nentes para cada dispositivo, na medida em que ocorrem devido a desvios de parâmetros durante o processo de fabrico e geralmente são compensadas por trimming. Vários efeitos CMOS foram estudados, tais como tensão de threshold (VT) e zero coeficiente de temperatura (ZTC).

O uso de osciladores com topologias simples para que possam ser totalmente integrados no chip é possível, mas não fornece qualquer compensação no que diz respeito às variações PVT. Como tal, para realizar um oscilador com maior confiança, um esquema de compensação deve ser integrado para que a frequência de oscilação possa ser estabilizada.

O principal objetivo deste trabalho é a implementação em CMOS de um oscilador estável e insensível a PVT adequado para plena integração no chip. A topologia de um oscilador em anel current-starved foi analisada tendo em consideração o comportamento PVT e variação da frequência para desvios de tensão de controlo e alimentação. Várias técnicas que ajudaram a obter, organizar e classificar os dados de forma eficiente e escalável são explicadas. Uma topologia foi desenvolvida para combinar dois conjuntos de linhas com características semelhantes de diferentes circuitos, contendo ganho, offset e coeficiente de temperatura.

Finalmente, a implementação completa de um oscilador totalmente integrado e compensado em PVT é apresentada com um erro máximo de 1.72%. Contendo um oscilador em anel

current-starved, um extractor de VT para a compensação de processo e temperatura, bem como duas

refer-ências de tensão integradas.

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Acknowledgements

To my supervisors, Cândido Duarte and Miguel Pina, without them would been impossible to achieve such a result. They were very helpful and outstanding on always trying to find new and clever ways to overtake the many problems found.

To my family which always gave me motivation throughout these years. To Pedro Coke for the initial help on how to setup and analyse a ring oscillator. To Daniel Oliveira and Américo Dias for the great moral and technical support.

To Microelectronics Students’ Group colleagues which gave me a good work environment. To the faculty Microelectronics Students’ Group and to SiliconGate for providing all the re-quired work infrastructure.

To the Cosmos for the privilege of being alive! ¨^

Henrique Cavadas

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“It’s fine to celebrate success but it is more important to heed the lessons of failure.” Bill Gates

“The most important single ingredient in the formula of success is knowing how to get along with people.” Theodore Roosevelt

“By failing to prepare, you are preparing to fail.” Benjamin Franklin

“Education is what remains after one has forgotten what one has learned in school.” Albert Einstein

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List of Figures

1.1 Typical schematic of an N-stage Single-Ended Current-Starved Ring Oscillator . 1

1.2 VT of an NMOS transistor as a function of temperature . . . 2

2.1 VT N extractor . . . 6

2.2 A three-terminal VT extractor circuit . . . 7

2.3 VT P extractor circuit . . . 8

2.4 IPTAT current generator . . . 9

2.5 A CMOS PTAT current generator . . . 9

2.6 VP extractor and VNextractor circuits from a voltage reference schematic . . . 11

2.7 Transconductance characteristic of an NMOS transistor . . . 12

2.8 Diode-connected transistor biased with PTAT current source . . . 13

2.9 Self-biased current reference . . . 14

2.10 Conventional voltage-mode Wheastone Bridge . . . 15

3.1 Illustrative example of the modified false-position method applied to the optimiza-tion of Vctr . . . 18

3.2 Ideal topology for matching RO’s control voltage with a PVT circuit . . . 21

4.1 Schematic of a 7-stage single-ended current-starved RO with dummy loads and a buffer . . . 26

4.2 Control voltage required for the same oscillation frequency of a 7-stage single-ended current-starved RO . . . 27

4.3 V_T and IDbehaviour with a fixed oscillation frequency of an 7-stage single-ended current-starved RO . . . 27

4.4 Frequency error of an 7-stage single-ended current-starved RO . . . 28

4.5 Null frequency error of an 7-stage single-ended current-starved RO . . . 29

4.7 Frequency variation in relation to Vctr and VDD variation of an 7-stage Single-Ended Current-Starved RO . . . 30

4.8 Vctrfor constant foscconsidering different temperature effects independently . . . 32

4.9 Control voltage required for the same oscillation frequency of a 7-stage single-ended current-starved RO . . . 33

4.10 VTand IDbehaviour with a fixed oscillation frequency of an 7-stage Single-Ended Current-Starved RO . . . 33

4.12 Null frequency error of an 7-stage single-ended current-starved RO . . . 35

4.14 Frequency variation in relation to Vctrand VDDvariation of an 7-stage single-ended current-starved RO . . . 36

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xii LIST OF FIGURES

4.15 Vctrvariation of an 7-stage single-ended current-starved RO . . . 37

4.16 Vctrfor constant foscconsidering different temperature parameter effects indepen-dently . . . 38

4.17 Typical block diagram of a N-stage differential RO . . . 40

4.18 Schematic of the implemented Differential RO blocks . . . 41

4.19 Control voltage required for the same oscillation frequency of a 7-stage differential RO . . . 42

4.20 Frequency variation in relation to Vctrand VDDvariation of an 7-stage differential RO . . . 42

4.21 Vctrfor the same foscconsidering different temperature parameter effects indepen-dently . . . 44

5.1 Simple |VTP| extractor circuit . . . 45

5.2 VREFlimits in function of m . . . 47

5.3 V_Oas a function of temperature for different m values . . . 47

5.4 VOand RO control voltage for different corners along the temperature . . . 48

5.5 VTextractor behaviour for different VREFand VDDas a function of m . . . 49

5.6 Straight lines slope for different VREFand VDD as a function of m . . . 49

5.7 Space between corners for different VREFand VDDas a function of m . . . 50

6.1 Block diagram of the implemented circuit for a PT compensated RO . . . 51

6.2 Schematic of the bandgap voltage reference . . . 52

6.3 Simulation results of the bandgap output voltage . . . 53

6.4 Schematic of the differential amplifier . . . 53

6.5 Frequency error of a RO with negative slope along temperature and process with-out any compensation . . . 55

6.6 Frequency errors of a compensated RO with negative slope at different compensa-tion phases . . . 56

6.7 Frequency error of the final circuit along temperature and process compensated using only BSIM models . . . 57

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List of Tables

4.1 Highest SVfctr range for typical process . . . 39

5.1 Illustrative example of the |VTP| extractor for oscillator compensation . . . 48

6.1 Differential amplifier behaviour along temperature and process variation . . . 54

6.2 Comparison of compensated oscillators . . . 58

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xvi ABBREVIATIONS and ACRONYMS

List of Abbreviations

BJT Bipolar Junction Transistor

CMOS Complementary Metal-Oxide Semiconductor

IC Integrated Circuit

IPTAT Inversely Proportional To Absolute Temperature

MOS Metal–Oxide–Semiconductor

MOSFET Metal–Oxide–Semiconductor Field-Effect Transistor

MSE Minimum Square Error

NMOS n-channel MOSFET

OPAMP Operational Amplifier

OTA Operational Transconductance Amplifier

PMOS p-channel MOSFET

PSRR Power Supply Rejection Ratio

PT Process and Temperature

PTAT Proportional To Absolute Temperature

PVT Process, Voltage and Temperature

RO Ring Oscillator

TC Temperature Coefficient

TPC Temperature and Process Compensation

VT Threshold Voltage

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Chapter 1

Introduction

A ring oscillator (RO) is a basic building block in CMOS integrated circuits (ICs). ROs can be used in applications such as phase-locked loops (PLL), clock recovery circuits for data communi-cations, disk drive read channels, on-chip clock distribution and integrated frequency synthesizers. The wide frequency tuning range, design simplicity, small silicon area, easy integration, and low power consumption are main factors for adoption of such oscillators.

The topology implemented in this thesis uses a single-ended current-starved RO that is de-picted in Fig. 1.1, the oscillation frequency ( fosc) can be obtained taking into consideration the slew rate, given by ratio of the current imposed and the capacitance at each node (I/C), number of inverters (N) in the chain and the switching voltage (Vsw) usually at the midrange of the power supply. f_osc= I 2NVswC (1.1) 1 2 N Vout Vctr

Figure 1.1: Typical schematic of an N-stage Single-Ended Current-Starved Ring Oscillator.

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2 Introduction

1.1 Problem Statement

As clock generation is a required and essential internal feature on almost any electronic system it should provide low frequency deviation. However, to ensure oscillation stability it is necessary to compensate process and temperature deviations which affect MOS device parameters.

Temperature and supply voltage changes may occur over time and can be caused by internal factors such as heat generated by the device or external such as environmental changes. Changes in process are, in contrast, static and permanent for each device, as they occur due to parameter deviations during the fabrication process and are usually compensated by trimming.

Due to the increasing integration -all in one IC- we propose a CMOS ring oscillator com-pensated in temperature and process. As such, by identifying the common variation factors of MOSFETs, we could better understand how to compensate for this. The temperature factors are easily studied because they are linear and well documented. While the process behaviour makes more sense to be done at circuit level as we know it will impose deviations on the device parame-ters. Of course, these factors are highly dependent on the technology; node size, foundry, process and etc.

The threshold voltage decreases approximately linearly with temperature [1, p.190], using the equation (1.2), where T0is the reference temperature and αV T is a constant. An illustrative example is shown in Fig. 1.2, where an NMOS transistor with ratio W /L = 2, operating in saturation, is simulated for obtaining VT at different temperatures.

VT(T ) = VT(T0) − αV T(T − T0) (1.2) −40 −20 0 20 40 60 80 100 120 0.32 0.36 0.4 0.44 0.48 0.52 Temperature ( °C ) V T (V)

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1.2 Proposed Approach 3

Another main temperature factor is the effective mobility [1, p.189], that depends on the tem-perature as follows: µ (T ) = µ (T0) T T0 −m (1.3) where the µ(T0) is the mobility at the nominal temperature and m a constant. It decreases expo-nentially with the temperature.

1.2 Proposed Approach

Let us name “compensation lines” to the set of control voltages (Vctr) across an arbitrary tem-perature range that provide the same frequency ( ftarget). For each temperature and voltage pair, the frequency variation slope can be obtained due to slight changes in Vctr1. The compensation strat-egy relies on an oscillator with low frequency variation in relation to the control voltage variation (S_Vf

ctr). This means that a slight change in the control voltage should produce only a minor change

in the oscillation frequency, even though temperature could affect it significantly. Our hypothesis is the following; if it’s possible to design a circuit producing an output voltage that matches the compensation lines, a PT-compensated oscillator can be implemented; even though there is not an exact matching because of its low SVfctr the frequency deviation will be low. This last point is

particularly important as if all possible process deviations are considered, the perfect matching becomes very difficult to achieve, plus it will always exist minor deviations due to parasitics or mismatch.

The proposed approach addresses an orthogonal tuning methodology, to allow a designer de-termine the temperature, process and voltage behaviours almost independently. As there is always some minor influence between any of these effects, this approach is coined “quasi-orthogonal compensation”.

The process sensing circuitry consists of a simple VT Extractor circuit as the compensation lines follow the VT intrinsic behaviour over process and temperature. However, due to other factors as the space between corners and different temperature slope additional circuitry was added for gain and offset adjustment. For each PVT point it exists a delta of Vctrdeviation and consequent error estimation, the oscillator with lower maximum error is chosen.

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4 Introduction

1.3 Organization of this Dissertation

In the next chapter it’s presented several CMOS effects and circuits for their compensation or extraction such as threshold voltage and zero temperature coefficient.

In chapter 3 some techniques used on different analysed circuits are explained which helped to obtain, organize and classify data in a efficient and scalable manner. For example, the modi-fied false-position method helped to obtain the RO’s control voltage efficiently for a given target oscillation frequency, allowing to explore different ROs and specific transistor influence.

Chapter 4 covers a selected set of RO topologies, single-ended and differential, to study the circuits and to provide general comparison on key performance metrics.

In chapter 5 the focus shifts to compensation circuits, where circuits with a behaviour similar to the RO’s control voltage are studied.

Chapter 6 presents the final topology used and the results obtained at the different implemen-tation phases.

Lastly, chapter 7 provides the insights and conclusions that arise from the development of this work, as well as stating future work on the topic.

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Chapter 2

Literature Review

Different architectures can be found in the literature of CMOS oscillators. The performance can differ in terms of temperature, power-supply susceptibility, phase noise and jitter - as well as power consumption.

In order to compensate in temperature and process an oscillator and also to gain more

knowl-edge, several CMOS effects have been studied in this chapter such as VT sensing and Zero

Tem-perature Coefficient (ZTC).

2.1 Threshold Voltage (V

T

) Sensing

Techniques using VT sensing can be applied for precision and reference voltages, thermal

sensors for on spot temperature measurement alongside other IC blocks, increasing the reliability and accuracy of measurements and reducing unpredictable effects on circuit performance.

2.1.1 V_T Extractor

In this section self biased CMOS VT extractors are presented, eliminating the need of a ref-erence voltage (VREF) input terminal, directly producing an output voltage in function of VT of a MOS transistor, eliminating the former way of obtaining the transconductance characteristic and subsequent calculations, being these key circuits for supply independent voltage generation.

Early, in [2], is presented a method for extract an integer multiple of the threshold voltage, achieving very good power supply rejection. It is presented two symmetric circuits for both PMOS and NMOS VT extractor, VT N and VT P, respectively. For simplicity reasons only the VT N extractor is analysed here, it is shown in Fig. 2.1.

All transistors operate in the saturation region and all the subtracts are connected to the sources, so it is assumed that all transistors have the same threshold voltage. The circuit is has an array of m+ 1 NMOS devices (ME1− MEm+ MF), a cascode current source (transistors MA− MD) which

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6 Literature Review

generates the bias current (IR) that is scaled through a resistor (R) and mirrored by MG− MH. The output is referenced to VDDand can be expressed by:

VDD−Vout= m

∑

i=1 VGSEi ! −VGSF = m VT+ r IE SEK ! − VT+ r IF SFK ! (2.1) where S is the W/L ratio and K is 1₂µnCox. Assuming that the Ks are equal and if

IF IE =SF SE m2 (2.2) then VDD−Vout= VT(m − 1) (2.3)

being Voutreferenced to VDD, supply independent and a multiple integer of VT. To the current ratio imposed in (2.2) the following transistor W/L ratio condition should be applied:

SA SB =SH SG 1 m2 SE SF + 1 ! (2.4) VDD M_E1 MEm MC MA MG R MD MB MH MF V_out

Figure 2.1: VT N extractor circuit proposed in [2].

In [3] is proposed a modified VT extractor which its circuit is presented in Fig. 2.2. Assuming that the voltage at M11’s gate is VREF, the current flowing trough M11’s drain is equal to K₂(VREF− VT)2. M12and M13are identical with the W/L ratio 4x bigger than M11being the current at M13’s drain equal to 4K₂(VO

2 − VT)

2_{then by equalizing the currents V}

O= VREF+ VT. The last block is a differential amplifier (M21and M22) which subtracts VREF of VOresulting in Vout= VT.

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2.1 Threshold Voltage (VT) Sensing 7 VDD M31 M32 M₁₄ M₁₁ M15 M₁₂ M13 M₂₁ Vout M₂₂ VO V_REF

Figure 2.2: A three-terminal VT extractor circuit proposed in [3].

Another VTextractor [4] is analysed here, its circuit is shown in Fig. 2.3. Let us assume that T2 operates in linear (triode) region and T1and T3in saturation region. Analysing T3 independently of T1and T2we obtain the equations (2.5) and (2.6), while full circuit gives (2.7).

|VDS2| = √ 2Ir 1 K1 +1 + a K2 r 1 K1 (2.5) |VGS3| = |VT| + √ 2Ir 1 + a K3 (2.6) |V_DS3| = |V_GS3| − |V_DS2| (2.7)

Combination of the above equations gives us the desired value of VDS2(2.8) which if applied results in |VDS3| = |VT| or Vout= VDD−VT, by equalization of (2.5) and (2.8) the condition (2.9) is obtained.

The equation (2.9) has many solutions with different transistor and current ratios. The con-dition of saturation imposes that the bias current should satisfy the concon-dition (2.10). Simulation results shows that the variation of current I with the temperature does not introduce errors in the measure of VT. |V_DS2| =√2Ir 1 + a K3 (2.8) r 1 K1 +1 + a K2 r 1 K1 =r 1 + a K3 (2.9) √ 2Ir 1 + a K3 ≤ |VT| (2.10)

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8 Literature Review VDD T₃ V_out T₂ T₁ I aI

Figure 2.3: VT Pextractor circuit proposed in [4].

2.1.2 Voltage Reference

A precision voltage reference circuit is very important in the design of ICs such as oscillators which are required to be stable over process, power supply voltage, and temperature variations.

In this section supply and temperature independent voltage sources are analysed.

A current mode CMOS voltage reference is proposed in [5], where two currents are generated, one that is proportional to the absolute temperature (PTAT) and another that is inversely propor-tional to absolute temperature (IPTAT), then they are scaled and summed into a resistor (Rsum) to generate a first order temperature independent voltage (VREF) given by 2.11.

VREF= (IPTAT+ IIPTAT) × Rsum (2.11)

The IPTAT current generator, shown in Fig. 2.4, uses a PMOS threshold voltage extractor circuit that has been analysed in the previous section, 2.1.1, the VT is buffered and applied across a resistor to generate the current IIPTAT:

I_IPTAT=VT

R0

(2.12) A CMOS PTAT generator consists in two bipolar transistors that are diode-connected substrate pnp’s, 4 MOSFETs form a feedback loop which forces the NMOS’ sources to be at equal potential, then the current is mirrored for summing with the IPTAT current, this circuit is shown in Fig. 2.5. The PTAT current (IPTAT) is given by (2.13), where k is Boltzman’s constant, q is the electron charge, T is absolute temperature, N is the emitter area ratio of Q1 to Q2, and a is the W/L ratio

of M5 to M1. The PTAT circuitry has a trimming scheme, once VT and consequently the IPTAT

current varies with the process.

IPTAT= a T k qRp

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2.1 Threshold Voltage (VT) Sensing 9 VDD M3 M₂ M₁ − + M6 IIPTAT R0 M₄ M5 Vbias

Figure 2.4: IPTAT current generator proposed in [5].

VDD M₁ M₃ Rp Q₁ M₂ M₄ Q₂ M₅ IPTAT

Figure 2.5: A CMOS PTAT current generator proposed in [5].

The resistors appear as ratios on the VREFequation, allowing the TCs of the matched resistors to approximately cancel and do not affect the temperature coefficient of the output voltage.

With the same architecture and a very similar implementation is proposed, in [6], a new design

that exhibits many performance improvements, presenting 9.3ppm/◦C over [5]’s 36ppm/◦C for

simulated TC.

The Vbias of the IPTAT generator is now biased from the PTAT generator instead of from

the output, such that all the circuit operates with the same base supply variations. More, it is implemented a high resolution trim network of 6-bits allowing fine adjustments to set the voltage variation with temperature to minimum.

In [7] is proposed a voltage reference circuit that uses proportional to the threshold voltage of both PMOS and NMOS devices, that are subtracted to form a temperature independent reference voltage.

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10 Literature Review

The Fig. 2.6a shows a block of the voltage reference circuit that generates a voltage (VP) linear with the temperature (threshold voltage) given by (2.14). MP1 operates in the saturation region while MP2 operates in the triode region by scaling R1 and R2 properly, the threshold voltages of MP1 and MP2 are considered equal. MP3serves as a start-up device, injecting current into MP1the OPAMP will start to operate then MP3is cut off completely and does not affect normal operation.

VP= 1 − α(1 + β ) + (1 − α)p1 + β 1 − α2_{(1 + β )} VT p (2.14) where α = R2 R1+ R2 (2.15) and β =W1 L1 L2 W2 (2.16)

The circuit of the VN extractor block from a voltage reference schematic proposed in [7],

shown in Fig. 2.6b, it is very similar with the VP extractor block just having NMOS instead of

PMOS devices. However, different equations are applied, here both MN1and MN2 operate in the

saturation region by scaling R3and R4 properly. Again, MP4 serves as a start-up device. VN can be expressed as: VN= VT n− p βVT n0 1 − α(1 +pβ ) (2.17) where α = R4 R3+ R4 (2.18) and β =W1 L1 L2 W2 (2.19)

Therefore, VP and VN are multiples of VT and independent of mobility, being strongly lin-ear with the temperature. Then, VP and VP are subtracted with different weights using a simple OPAMP, as they have both negative temperature coefficients (TCs), forming a zero TC voltage. The measured TC of the reference voltage as a function of temperature and power supply is of 33ppm/◦C.

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2.2 Zero Temperature Coefficient (ZTC) 11 Vstrp MP3 − + _V P MP1 MP2 R1 R2 (a) Vstrp MP4 − + _V N MN1 MN2 R3 R4 (b)

Figure 2.6: (a) VP extractor and (b) VN extractor circuits from a voltage reference schematic pro-posed in [7].

2.2 Zero Temperature Coefficient (ZTC)

MOS transistor characteristics are strongly temperature dependent [1], being the threshold voltage and the mobility the main temperature effects. As the temperature increases, both the threshold voltage and the mobility decrease, however with opposite effects given by (2.20), the drain current of an NMOS transistor in the saturation region.

ID= 1 2µnCox W L(VGS−VT) 2 _(2.20)

The variation of drain current with the gate-source voltage (transconductance characteristic) at different temperatures have a common intercept point, known as the ZTC point, with parameters (VGS, ID). If transistor is biased to this point by a current source, then the gate-source voltage will not depend on temperature, which means that the threshold voltage and the mobility are mutually compensated. This can be used for design of temperature stabilized voltage and current sources.

An illustrative example is shown in Fig. 2.7. Please note that for lower drain currents the threshold voltage dominates the behavior as the drain current increases with temperature, on the other hand, for higher drain currents, above the ZTC point, the mobility dominates.

A simple temperature independent voltage reference using a diode-connected MOS transistor biased with a PTAT current source below its ZTC point is proposed in [8] and shown in Fig. 2.8. Transistors Ms1− Ms3 form the start-up circuit for the PTAT current source (transistors M1− M5 and resistor Rb) and the diode-connected transistor is M6.

M6in the saturation region can have the gate-source voltage expressed as:

VGS(T ) = VT H0− αV T(T − T0) + K( T T₀) m 2p_I D(T ) (2.21)

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12 Literature Review 0.8 0.84 0.88 0.92 0.96 1 4 5 6 7 8 9 10 11 V GS (V) I DS ( µ A) T= −20°C T= 0°C T= 20°C T= 40°C T= 60°C T= 80°C

Figure 2.7: Transconductance characteristic of an NMOS transistor for different temperatures.

where K= s 2 µ0CoxW_L (2.22) If the temperature increase from T0by a small amount of δ T to T0+ δ T , the gate-source voltage can be expressed as:

δVGS∼= δ T h − αV T+ λ 2 m T0 + γ i (2.23)

where λ = K√ID0 and γ is a positive constant. Hence, if a PTAT current source has the design

parameters λ and γ satisfying (2.24), the VGS of M6(VGS6) biased with the current source can be temperature independent. λ 2 m T0 + γ= αV T (2.24)

Using a first order approximation the bias current is equal to:

IB= IB0[1 + γ(T − T0)] (2.25) where IB0= 2 Cox µ₀−1R−2_B0 r L4 W4 −r L3 W3 !2 (2.26) and γ = m T0 − 2αR1 (2.27) and Rb= RB0[1 + αR1(T − T0) + αR2(T − T0)2] (2.28)

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2.2 Zero Temperature Coefficient (ZTC) 13 should satisfy: r W5L1 L5W1 = αV T K√ID0(Tm0 − αR1) (2.29)

The circuit was simulated in the temperature range of -50 to 150◦C and it is able to operate with a sub-1 V power supply. The temperature stability of the gate-source voltage (VGS6) obtained in simulations is equal to 4 ppm/◦C, second order non-linearity limit an exact realization of PTAT current. VDD Ms1 Ms2 Ms3 M1 IB M3 Rb M2 M4 M5 Vout ID M6

Figure 2.8: Diode-connected transistor biased with PTAT current source proposed in [8].

A self-biased CMOS current reference topology based on the ZTC condition is proposed in [9] and it is shown in Fig. 2.9. An operational transconductance amplifier (OTA) implements a

feedback loop of a poly resistor (Rpoly) and an NMOS transistor (MZTC) operating in the ZTC

vicinity, this balances the temperature dependence of both Rpoly and MZTC. A PMOS mirror is

formed by M1− M4 for biasing with unitary gain and also exists a start-up circuit composed by M5− M7. By analysing the circuit the following equation is deducted:

R(T1)(IDF+ ∆Id) = R(T1)IREF= VOS+VGSF (2.30)

where VOSis amplified offset voltage, VGSF (2.31) and IDF (2.32) are the gate-source voltage and the drain current of MZTCat ZTC point, ∆Id represents a small variation in the drain current that results of operating at the ZTC vicinity and not exactly at the ZTC point of operation.

VGSF= VT(T0) + nVSB− αVTT0 (2.31) IDF= W L µn(T0)T02Cox 2n α 2 VT (2.32)

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14 Literature Review

The poly resistor thermal dependence can be approximated as (2.33).

R(T1) ≈ R(T0)(1 + α1(T1− T0)) (2.33)

The first step is the definition of IREF, then the correspondent value of resistor R(T0) (Rpoly) and finally the size of the transistors. The effective temperature coefficient simulated for typical device parameters is of 15 ppm/◦C from -40 to 85◦C and the inclusion of process and mismatch variability effects results in a maximum of 100 ppm/◦C.

VDD M₄ IREF M₁ Rpoly M₂ M_ZTC M3 VDD M₇ M₆ M₅ − + Ibias

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2.3 Wheatstone Bridge 15

2.3 Wheatstone Bridge

Wheatstone bridge is used, for many years, for evaluating small resistance changes. The con-ventional voltage-mode and well known Wheatstone bridge [10] consists of 4 resistors as shown in Fig. 2.10.

If the all resistors are equal (Ri= R) and R2with a slightly increase of ∆R then the bridge is balanced: Vout= VDD ∆R 4R + 2∆R≈ VDD ∆R 4R (2.34) V_DD R4 − R3 R1 + R2 Vout

Figure 2.10: Conventional voltage-mode Wheastone Bridge.

Temperature sensors can be achieved using this simple topology and technology that enables more than one layer for resistors, has proposed in [11], using BiCMOS technology.

For that the resistors R1and R3 were realized in polysilicon resistor layer (RPOLY) and base diffusion layer (RDIFF) for R2and R4.

Vout= R2 R₁+ R2 − R3 R₃+ R4 VDD (2.35)

assuming that R1= R3= R0[1 + α1(T − T0)] and R2= R4= R0[1 + α2(T − T0)] , where αi repre-sents different resistor TCs, one obtains that

Vout=

VDD(α1− α2)(T − T0) 2 + (α1− α2)(T − T0)

(2.36) being the output voltage of the bridge temperature dependent. However, not totally linear as the resistor quadratic components are not compensated.

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Chapter 3

Characterization Techniques

In this chapter some techniques used on different circuits are explained which helped to ob-tain, organize and classify data in a efficient and scalable manner. The modified false-position method (3.1) was implemented to characterize the RO PVT behaviour efficiently for a given target oscillation frequency, allowing to explore different ROs and specific transistor influence.

For classification a coefficient of determination (3.2), pronounced R squared, was implemented allowing to know the goodness of fit of a line for instance RO’s control voltage, and find straight, parallel and evenly spaced lines. An ideal topology (3.3) was developed for matching two sets of those lines with the same features of different circuits. Analysis of the RO’s supply and control voltage deviation effect on frequency (3.4) was done allowing good error estimation and to find the most insensitive oscillators.

3.1 Modified False-Position Algorithm

A modified false-position (or “regula falsi”) method, sometimes called the Illinois algorithm, is used to find the voltage for which the desired oscillation frequency ( ftarget) is achieved1. This avoids the use of the Vctrsweep that implies a large number of simulations. Instead, as depicted in Fig. 3.1, the solution is attained in just a few steps. This is only possible because of the monotonic-ity of the function fosc(Vctr) and a single root in the interval considered containing fosc− ftarget. Since in some cases an oscillation frequency cannot be found for the initial values (e.g. due to convergence issues), the algorithm applies also some modifications to the interval limits. Alg. 3.1 shows the method’s pseudo code algorithm to take into consideration for the convergence fails mentioned above.

The control voltage should be in the range Vctr∈ [0 : Vdd− |Vt,p|], i.e. the sub-threshold in the PMOS regulating the current is avoided because of the resultant small currents. These imply an os-cillation frequency almost null since the sinked/sourced current is not enough to charge/discharge

1_{The Illinois algorithm was preferred to the false position method and to the most popular Newton method to}

guarantee super-linear convergence and to ensure predefined limits for the control voltage range, respectively.

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18 Characterization Techniques 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 −30 −20 −10 0 10 20 30 40 50 Control Voltage (V) Oscillation Frequency − 25.0 (MHz) 2 no convergence → 1 2 3 4 5 6789

Figure 3.1: Illustrative example of the modified false-position method applied to the optimization of Vctr.

the inverter loads. Also, in order to avoid similar situations the algorithm implements an initial setup up to the first control voltage values (Vctr,l and Vctr,r) using Vadjust to ensure that both ini-tial frequencies fosc(Vctr,l) and fosc(Vctr,r) exist and are greater and lower than ftarget, respectively. When the difference between fosc(Vctr,l) and fosc(Vctr,r) is lower or equal than the defined tolerance ( ftol) it stops, or simply when it reaches the maximum number of iterations (max_iter) meaning that no desirable value of fosc was found. For each iteration a new Vctrvalue is computed by the formula stated at line 25 of Alg. 3.1, then based on the signal of [ fosc(Vctr,c) − ftarget] new values of

[Vctr,l,Vctr,r] will be defined: if greater than zero Vctr,l= Vctr,c and Vctr,r= Vctr,cotherwise.

An example of the linear behaviour of control voltage along temperature and process variation for the same oscillation frequency can be seen in Fig. 4.9.

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3.1 Modified False-Position Algorithm 19

Algorithm 3.1: Algorithm for the modified false-position method

1 define: V_adjust(used for finding initial V_ctrpoints), f_tol(condition to stop)

2 Vctrinterval [Vctr,l,Vctr,r] = [0,Vdd− |Vt,p|], max_iter (maximum number of iterations)

3 run_simulation()

4 while fosc(Vctr,l) − ftarget< 0 do

5 Vctr,l= Vctr,l−Vadjust 6 run_simulation() 7 while ! fosc(Vctr,l) do 8 Vctr,l= Vctr,l+Vadjust/10 9 run_simulation() 10 end 11 end

12 while fosc(Vctr,r) − ftarget> 0 do

13 V_ctr,r= V_ctr,r+V_adjust 14 run_simulation() 15 while ! fosc(Vctr,r) do 16 V_ctr,r= V_ctr,r−V_adjust/10 17 run_simulation() 18 end 19 end 20

21 while iteration ≤ max_iter do

22 if abs[( fosc(Vctr,l) − fosc(Vctr,r)] ≤ ftolthen

23 end of algorithm ⇒ save data

24 end

25 Vctr,c=

fosc(Vctr,r)×qr×Vctr,l− fosc(Vctr,l)×ql×Vctr,r

fosc(Vctr,r)×qr− fosc(Vctr,l)×ql

26 run_simulation()

27 if fosc(Vctr,c) × fosc(Vctr,l) > 0 then

28 V_ctr,l= V_ctr,c

29 if fosc(Vctr,c) × fosc(Vctr,l) > 0 in the previous iteration then

30 qr= 1/2

31 else

32 qr= 1, ql= 1

33 end

34 end

35 if fosc(Vctr,c) × fosc(Vctr,r) > 0 then

36 V_ctr,r= V_ctr,c

37 if fosc(Vctr,c) × fosc(Vctr,r) > 0 in the previous iteration then

38 ql = 1/2

39 else

40 qr= 1, ql= 1

41 end

42 else

43 end of algorithm ⇒ save data

44 end

45 iteration= iteration + 1

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20 Characterization Techniques

3.2 Coefficient of Determination

For better fit and analyse the RO’s control voltage (Vctr) a decision was made to look for straight, parallel and evenly spaced lines. The R-squared (R2) metric was used which tell us how well the data fits a model and by changing the linear regression model different line characteristics can be found.

The adjusted R-squared was also considered but the R2was chosen because the sample size

and the number of independent variables are fixed plus the R2is more a measure of fitting while the adjusted R2is more a comparative measure. R2is given by the following equation where SSres is the residual sum of squares and SStot the total sum of squares.

R2= 1 −SSres SStot

(3.1)

3.2.1 Straight lines

An ordinary least-squares regression with a temperature vector (Ti) as the regressors and Vctras the function response (3.2) was performed, providing the polynomial coefficients (βi) for a straight line along temperature (3.3), this line is straighter for the highest values of R2.

fi= Vctr(Ti) (3.2)

yi= β1Ti+ β0 (3.3)

The least-squares method minimizes the sum of squared residuals, but still does not ensure that the mean of the residuals will be exactly zero (unbiased) and the R-squared method cannot determine whether the coefficient estimates are biased, which is why the residual plots must be assessed for unwanted residual patterns. Furthermore, all lines were plotted for visual analysis, ensuring proper behaviour and giving insights regarding the R2factor adjustment. Notice that just lines with very high R2are straight, for reference the selected lines have R2greater than 0.9992.

3.2.2 Parallel lines

Let us assume n straight lines for instance from different process corners, each one of those has slope information (β1) from the above method (3.3). An ordinary least-squares regression is performed again but using a different model, the vector of predictors is a evenly spaced integer vector (Xi), for example (3.4), and a sorted vector with the slopes (β ) is created representing the function response (3.5), the result of the regression is a line with the same format as (3.6).

Xi= [−n/2, ..., 0, ..., n − n/2 − 1] (3.4)

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3.3 Matching lines 21

zi= α1Xi+ α0 (3.6)

To ensure the n lines are parallel zi should be a straight and parallel line to the abscissa axis which is guaranteed if R2 is high and the line’s slope (α1) is low. Limit factors are used and adjusted by doing visual analysis for α1and R2limits.

3.2.3 Evenly Spaced lines

As with the parallel lines method let us assume n straight or parallel lines, each one with offset information at 0oC (β0) from the method (3.3). An ordinary least-squares regression is performed again, the vector of predictors is a evenly spaced integer vector (Xi), for example (3.4), and a sorted vector with the offsets (γ) is created representing the function response (3.7), the result of the regression is a line with the same format as (3.8).

fi= γ(Xi) (3.7)

si= λ1Xi+ λ0 (3.8)

To ensure the n lines are evenly spaced si should be a straight line which is guaranteed if R2 is very high. A factor for the R2limit is used and adjusted by doing visual analysis which is done for all solutions.

3.3 Matching lines

An ideal topology was developed for matching two sets of straight, parallel and evenly spaced lines with different characteristics. The schematic in Fig. 3.2 represents a possible application for this topology where a RO, a block of gain, another for sum, a voltage source with temperature slope and a PVT generator that should produce process, voltage and temperature behaviour similar with the RO requirements.

PVT

generator + AV RO

α T + vOS

V_PVT(T ) X₂(T ) V_RO(T )

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Considering the typical and linear behaviour along temperature (T ) we get the following equa-tions, VROrepresents the RO’s control voltage needed for stable oscillation.

VPVT(T ) = a1T+ b1

X2(T ) = a2T+ b2= (a1+ α)T + b1+ vOS VRO(T ) = aoT+ bo= X2(T )AV

(3.9)

Imposing that with the following equation,

aoT+ bo= [(a1+ α)T + b1+ vOS]AV (3.10)

the voltage gain (AV) and offset (VOS) can be deduced:

AV = ao a1+ α v_OS= bo AV − b₁ (3.11)

This result applies only for one line (typical process) and gives us a freedom degree, that is the temperature slope (α) of the voltage source is not required or can be used in conjunction with the gain and offset for easiest adjustment.

By applying the same reasoning for another line (VPVTc) representing a process corner which basically it’s the same as typical with an offset (C1) as shown below:

V_PVTc(T ) = a1T+ b1+C1 VROc(T ) = aoT+ bo+Co

(3.12)

Imposing that with the following equation,

aoT+ bo+Co= [(a1+ α)T + b1+C1+ vOSc]AV c (3.13)

the voltage gain (AV c) and offset (VOSc) for the corner can be deduced as: AV c= ao a1+ α vOSc= bo+Co AV c − b1−C1 (3.14)

the gain is the same as 3.11 and if imposed that VOSdoes not change with process we get:

V_OS= VOSc⇒ AV = Co C1 = ao a1+ α (3.15)

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3.4 OAT Local Sensitivity Analysis 23

The temperature slope is then obtained complementing all circuit parameters:

α = ao C1 Co − a1 AV = ao a₁+ α vOS= bo AV − b1 (3.16)

With this topology other process corners can be matched flawlessly as well, simply by respect-ing the rule of berespect-ing parallel and evenly spaced. Please note that if the space between corners is the same on both circuits (C1= Co) the coefficient of temperature can be suppressed (α = 0).

3.4 OAT Local Sensitivity Analysis

It became crucial to understand the influence of mismatching lines, that is the weight that deviations had on a giving oscillator’s frequency error. This would allow to have good error prediction for a given compensation circuit. First, let us consider that the frequency relative error is given by ε f (%) = fosc− ftarget ftarget × 100 = ∆ f ftarget × 100 (3.17)

The RO’s Vctrand VDDvoltages influence on the frequency was done using one-at-a-time (OAT) and local sensitivity methods in conjunction. That is each variable was analysed independently at some fixed point of their input space. The OAT method permits to have good comparative indexes

of Vctr and VDD independently, this can be done for minor RO voltage deviations which are our

goal. The local method was used due to the RO’s linear response, again, for minor deviations and for faster simulation time. The RO’s linear response was proved by using different fixed points.

The nominal values of Vctrand VDDtogether ensure no frequency error. Let us denominate V0 a fixed value different than the nominal value, then the voltage variations can be described as:

∆Vctr= Vctr0 −Vctrnom ∆VDD= VDD0 −VDDnom

(3.18)

The variation’s slope formula can be written as follows:

S_Vf ctr = ∂ f ∂Vctr Vctr0 = ∆ f ∆Vctr S_Vf DD= ∂ f ∂VDD V0 DD = ∆ f ∆VDD (3.19)

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Then the estimated frequency deviation can be written as follows: ∆ f (Hz) = ∆VDD× S

f

VDD− ∆Vctr× S

f

Vctr (3.20)

An increase in VDDprovides a positive change in frequency while Vctrhas the opposite behaviour. Please note that an RO has different values of variation’s slope at different temperatures this will be further analysed in Chapter 4.

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Chapter 4

CMOS Ring Oscillators

The RO can be fitted in the most simplest of approaches. Several variations are described in [12], despite of its structural simplicity, the CMOS RO can be implemented in different flavours. In fact, the basic inverter chain can be translated into more elaborated designs in which the inverter is driven by a current sink/source to build what is known as current-starved RO. Also, the current source can be applied using only one of the two, that are either a current sink or source. Another alternative is to use the current sink/source as the inner cells and switch them, allowing different performance properties.

In this chapter will be analysed two RO topologies single-ended and differential, taking into consideration PVT behaviour and frequency variation to control and supply voltage deviations. The techniques used to obtain these characterization are described in detail on chapter 3.

An RO requires a phase shift of 2π and unitary voltage gain to ensure self-sustained oscillation, generically, the frequency of oscillation is given by

f_osc= Ictr 2Ntd

(4.1) where N is the number of delay stages and td the time delay of each element. As such, each stage must provide a phase shift of π/N and the remaining π phase shift is provided by a DC inversion. Meaning that for single-ended stages an odd number of stages is necessary, otherwise, the RO with differential stages can have odd or even number of stages if the DC inversion is ensured.

4.1 Single-Ended Current-Starved RO

Multiple analysis have been done such as input MOS behaviour, frequency variation to control and supply voltage deviations, error estimation and temperature parameters influence on two ROs with straight and parallel compensation lines. One RO has compensation lines with positive slope

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26 CMOS Ring Oscillators 1 2 7 M1 I_ctr Vctr V_out

Figure 4.1: Schematic of a 7-stage Single-Ended Current-Starved RO with dummy loads and a buffer.

and another with negative slope, in order to compare them. Greater focus was given to the error estimation and frequency variation slope to PVT variations, as it presents a great metric on which RO is more appropriate to chose.

The two single-ended current-starved ROs analysed under this section have 7 stages, 6 stages have a dummy load and the output stage has a buffer, which have the same size so that each stage node has the same capacitance independently of the output circuit. The schematic can be depicted in Fig. 4.1. The ftarget considered was 25MHz and the supply voltage (VDD) 2.8V , the value of

V_DDwas chosen due to initial simulations which showed that with higher supply voltages bigger

sets of oscillators with straight compensation lines are available1.

4.1.1 Positive Slope

With this topology and technology was very cumbersome to find straight compensation lines with positive slope, however that has been suppressed by using buffer and dummy loads with different parameters (W/L) than the core RO inverters. Due to this requirement well defined PMOS and NMOS W/L ratios were imposed for good duty cycle. Smaller buffer/dummy loads device parameters provide a larger set of available oscillators with straight compensation lines, however it increases the frequency variation slope to Vctrdeviations. The example shown here is from a set with the lowest frequency variation slope (SVfctr), the Vctrrequired for a stable oscillation is depicted

in Fig. 4.2.

The RO has only MOS devices, the technology models include corners for fast and slow cases of NMOS and PMOS variations, resulting in four corners: fastN-fastP (FF), fastN-slowP (FS), slowN-fastP (SF) and slowN-slowP (SS), as well as the typical corner (TT), this denomination will be used from now on.

As we can observe from Fig. 4.2 the compensation lines are quite straight and parallel which

were obtained using the modified false-position algorithm (3.1) and then R2 (3.2). For each of

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4.1 Single-Ended Current-Starved RO 27 −40 −20 0 20 40 60 80 100 120 1.75 1.8 1.85 1.9 1.95 2 2.05 Temperature ( °C) V ctr (V) FF SF TT FS SS

Figure 4.2: Vctr required along temperature and process variation for the same oscillation fre-quency (25MHz).

those points (temperature, process and Vctr) the VTand drain current (ID) of the control transistor M₁were extracted, their behaviour is shown in Fig. 4.3. The VTis very linear along temperature and in process corners being quite similar with the Vctrrequired for stable oscillation while the ID has usually a behaviour difficult predict. This behaviour boosted a more thorough analysis on a VT extractor (chapter 5) with the intuit of compensate the RO.

0 50 100 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 Temperature ( °C) |VT | (V) FF SF TT FS SS (a) VT 0 50 100 −33 −32.5 −32 −31.5 −31 −30.5 −30 −29.5 −29 Temperature ( °C) ID ( µ A) FF SF TT FS SS (b) ID

Figure 4.3: VTand IDof transistor M1along temperature and process variation for the same oscil-lation frequency (25MHz).

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28 CMOS Ring Oscillators

4.1.1.1 Error Sensitivity

In order to understand the frequency deviation, different variations have been performed to V_DDand Vctrat different temperatures for the typical process corner. The frequency relative error is calculated using the formula 3.17 where foscis the frequency measured by simulation and ftarget is in this case 25MHz. Considering the nominal VDDand Vctras the values at which the oscillation frequency is equal to ftarget (zero error), the RO was re-simulated with different VDD and Vctr values. These values result by adding to a nominal value a deviation in percentage of its same nominal value, the graphics’ abscissa is depicted as error of VDD or Vctr which stands for this deviation of VDDor Vctr, respectively. −4 −2 0 2 4 −60 −40 −20 0 20 40 60 εV ctr (%) εf (%) T = −41°C T = −23°C T = −5°C T = 13°C T = 31°C T = 49°C T = 67°C T = 85°C T = 103°C T = 121°C (a) εVDD= 0% −4 −2 0 2 4 −40 −20 0 20 40 60 80 εV ctr (%) εf (%) T = −41°C T = −23°C T = −5°C T = 13°C T = 31°C T = 49°C T = 67°C T = 85°C T = 103°C T = 121°C (b) εVDD= 1% −3 −2 −1 0 1 2 3 −50 0 50 εV DD (%) εf (%) T = −41°C T = −23°C T = −5°C T = 13°C T = 31°C T = 49°C T = 67°C T = 85°C T = 103°C T = 121°C (c) εVctr= 0% −3 −2 −1 0 1 2 3 −60 −40 −20 0 20 40 εV DD (%) εf (%) T = −41°C T = −23°C T = −5°C T = 13°C T = 31°C T = 49°C T = 67°C T = 85°C T = 103°C T = 121°C (d) εVctr= 1%

Figure 4.4: Frequency error along temperature for typical process.

In Fig. 4.4 four illustrative examples are shown of how the frequency error varies by sweeping VDDand Vctr independently, in Fig. 4.4a and 4.4b VDDis fixed and Vctris swept while in Fig. 4.4c and 4.4d Vctris fixed and VDD is swept. Please note that for each temperature there is a different nominal value of Vctr(Fig. 4.2) so for a given percentage deviation of the nominal Vctralong the temperature the real deviation value is different for each temperature.

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4.1 Single-Ended Current-Starved RO 29

An increase on Vctrdecreases the frequency while VDDhas the opposite behaviour, both effects happen due to the increase of M1’s |VGS| and consequent drain current which is then mirrored by the NMOS current mirror, more current imposes a faster switching time on the inverters and consequently higher frequency. As expected, when the fixed variable is equal to their nominal value and the swept variable has the nominal value as well the frequency error is zero, see Fig. 4.4a and 4.4c. For each temperature there are different error values, the lowest temperature has always highest error until the point they intercept of zero error, this behaviour will be analysed with more detail ahead.

If VDD increases 1% of its nominal value then the Vctr has to increase around 1.75 times to compensate the error, see Fig. 4.4b, on the other hand if Vctr increases 1% then the VDD has to increase around 0.75 times to compensate the error, see Fig. 4.4d. This clearly indicates that in percentage the VDD has a stronger influence on the frequency deviation relatively to Vctr. Fig. 4.5 has a more detailed illustration of this behaviour, where for a given deviation of VDD or Vctr it is possible to identify how to vary the other voltage to compensate and have zero frequency error. The relation between VDDand Vctris equal for any temperature until ±1% because as shown before the voltage values intercept at zero error when the temperatures invert, for higher deviations the temperature devious effects start to impose. However, this analysis is very helpful to quantity how to compensate supply deviations on the control voltage which clearly have to be amplified on an almost linear manner, the value in concrete is equal to slope of the plotted lines which is around 1.75 for this oscillator.

−3 −2 −1 0 1 2 3 −4 −2 0 2 4 εV DD (%) εV ctr (%) T = −41°C T = −23°C T = −5°C T = 13°C T = 31°C T = 49°C T = 67°C T = 85°C T = 103°C T = 121°C

Figure 4.5: Null frequency error of simulated RO along temperature variation for typical process.

Fig. 4.6 takes into consideration another approach that is if the circuit compensating the RO varies the output (Vctr) proportionally to the supply voltage how would the oscillator behave in terms of frequency deviation. For example, for a deviation 1% on the supply voltage a maximum error close to 5% is obtained. A linear behaviour is observed for each temperature, again being

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the lowest temperature that imposes the highest error, due to this linearity the weight has been quantified for the different temperatures by computing the slope of the straight lines in Fig. 4.6a. Fig. 4.6b depicts that slope which is nearly two times different between the extreme temperatures

under consideration −41 and 121oC.

−3 −2 −1 0 1 2 3 −15 −10 −5 0 5 10 15 ε_V DD, εVctr (%) εf (%) T = −41°C T = −23°C T = −5°C T = 13°C T = 31°C T = 49°C T = 67°C T = 85°C T = 103°C T = 121°C

(a) Frequency error of εVDD= εVctr

0 50 100 2.5 3 3.5 4 4.5 5 Temperature ( °C) Slope (b) Slope of εVDD= εVctr

Figure 4.6: Frequency error and respective slope along temperature for typical process.

Due to the linearity observed in Fig. 4.4a and 4.4c, which is a general behaviour, the frequency variations in relation to Vctrand VDDvariation (SVfctr and S

f

VDD) are possible to be calculated using

the equation 3.19. 0 50 100 60 80 100 120 140 160 180 Temperature ( °C) ∆ f / ∆ V ctr (KHz/mV) FF SF TT FS SS (a) S_Vf

ctrwith a fixed variation of 10mV around the nominal

Vctr(±5mV ). 0 50 100 70 80 90 100 110 120 130 140 150 160 Temperature ( °C) ∆ f / ∆ VDD (KHz/mV) FF ±1% variation SF ±1% variation TT ±1% variation FS ±1% variation SS ±1% variation FF ±2% variation SF ±2% variation TT ±2% variation FS ±2% variation SS ±2% variation (b) S_Vf

DDwith different variations around the nominal VDD

(2.8V ).

Figure 4.7: Frequency variation in relation to Vctrand VDDvariation along temperature for different process corners.

Fig. 4.7a depicts S_Vf

ctrvariation along temperature for different process corners which is a good

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straight compensation lines. It is used a fixed value for the ∆Vctr (∆Vctr= Vctrnom± 5mV = 10mV ) again because of its linearity observed in Fig. 4.4a and for a simpler simulation algorithm.

S_Vf_DDis shown in Fig. 4.7b with two different VDDvariations (1% and 2%) it can be noticed that changes in VDD slightly affect the value of S

f

VDD. For a variation of ±3% around nominal VDD the

FF corner cannot be obtained due to the absence of oscillation. S_Vf

DD has a behaviour very similar

to the S_Vf_ctr just with a different absolute value.

A typical behaviour is that for the lowest temperatures the S_Vf

ctr and S

f

VDD have the highest

values. S_Vf_DD is generally lower than S_Vf_ctr which may seem to go against the graphic observed in Fig. 4.4, however this illusion happens due to the usage of different scales. The S_Vf

DD uses

the absolute scale (KHz/mV) while previous analysis use the voltage error in percentage of their nominal value, using the absolute scale is better for error estimation and to be a comparative metric as the nominal Vctrvalue is different for each temperature, process corner and RO.

4.1.1.2 Temperature Effects

To understand the influence of the MOS temperature effects the BSIM3v3.2 MOSFET model manual [13, A.6] was used to identify them, then the models’ parameters (NMOS and PMOS) were edited. The temperature effects considered were saturation velocity, mobility, VT, Rdsw and junction current, for each of those exist multiple independent parameters.

Fig. 4.8 depicts the Vctrrequired for the same fosc(25MHz) considering 4 different effects. In case of considering only a specific effect like in Fig. 4.8b, 4.8c and 4.8d the parameters associated with it maintain the original value while the others are changed to the value of zero.

In Fig. 4.8a the original compensation lines of Fig. 4.2 are compared with no temperature effects (except emission coefficient of junction) which results in a parallel line to the abscissa axis as there are no temperature effects to take into account. Fig. 4.8b reveals that the influence of the saturation velocity on the temperature slope is non-existent as it overlaps with the one with no temperature effects (Fig. 4.8a).

Fig. 4.8c shows that the compensation lines slope becomes positive considering only the

V_T temperature effect, which is the opposite slope of the VT behaviour along the temperature

(Fig. 1.2). This can be described as follows, considering the NMOS saturation formula (2.20) an

increase on the temperature, decreases the value of VT which increases the drain current, more

current means higher frequency so to compensate that the value of Vctrhas to increase.

Fig. 4.8d depicts the mobility temperature effect which changes the compensation lines slope to negative, this can be explained in a similar manner as before. An increase in temperature decreases the value of mobility which decreases the value of drain current, considering the NMOS saturation formula (2.20), less current means lower frequency and to compensate for that the value of Vctrhas to decrease.

Some points on the FF corner were not obtained, a possible cause could be that the simulation algorithm required more iterations to find a suitable foscwithin the tolerance given, this issue was not further researched. Please note that the rotation occurs at the nominal temperature (25oC)

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32 CMOS Ring Oscillators 0 50 100 1.7 1.75 1.8 1.85 1.9 1.95 2 2.05 2.1 2.15 Temperature ( °C) Vctr (V)

all temperature effects FF

SF TT FS SS

(a) No temperature effects and normal behaviour with all temperature effects 0 50 100 1.8 1.85 1.9 1.95 2 2.05 Temperature ( °C) Vctr (V) no temperature effects FF SF TT FS SS

(b) Saturation velocity effect and no temperature effects

0 50 100 1.7 1.75 1.8 1.85 1.9 1.95 2 2.05 2.1 2.15 Temperature ( °C) Vctr (V) no temperature effects FF SF TT FS SS

(c) VTeffect and no temperature effects

0 50 100 1.7 1.75 1.8 1.85 1.9 1.95 2 2.05 2.1 Temperature ( °C) Vctr (V) no temperature effects FF SF TT FS SS

(d) Mobility effect and no temperature effects

Figure 4.8: Vctrfor constant foscconsidering different temperature effects independently in com-parison with no temperature effects (emission coefficient of junction effect was not considered).

as expected. We can conclude that a solution with positive slope is more influenced by the VT

intrinsic behaviour than by the mobility.

4.1.2 Negative Slope

Contrary to the positive slope, with negative slope the RO inverts can have the same size as the dummy loads and buffer to find good compensation lines which is like the example that is presented and analysed here, Fig. 4.9 depicts the Vctr required along temperature for constant oscillation frequency.

It can be noticed that the SS corner is not as straighter as the other process corners, this is a typical limitation of the negative slope considering the methodology for matching lines (3.3) studied previously, however other advantages will arise.

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4.1 Single-Ended Current-Starved RO 33 −40 −20 0 20 40 60 80 100 120 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 Temperature ( °C) V ctr (V) FF SF TT FS SS

Figure 4.9: Vctr required along temperature and process variation for the same oscillation fre-quency (25MHz).

For each of point (temperature, process and Vctr) the VTand IDof the control transistor M1were extracted, their behaviour is shown in Fig. 4.10. Again, the VTis very linear along temperature for the different process corners while the IDhas usually a behaviour difficult predict.

0 50 100 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 Temperature ( °C) |VT | (V) FF SF TT FS SS (a) VT 0 50 100 −28 −27 −26 −25 −24 −23 −22 Temperature ( °C) ID ( µ A) FF SF TT FS SS (b) ID

Figure 4.10: VT and ID of transistor M1 along temperature and process variation for the same

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4.1.2.1 Error Sensitivity

In Fig. 4.11 four illustrative examples are shown of how the frequency error varies by sweep-ing VDD and Vctr independently, in Fig. 4.11a and 4.11b VDD is fixed and Vctr is swept while in Fig. 4.11c and 4.11d Vctris fixed and VDD is swept. Please note that for each temperature there is a different nominal value of Vctr(Fig. 4.9) so for a given percentage deviation of the nominal Vctr along the temperature the real deviation value is different for each temperature.

V_ctr and VDD impose the same frequency behaviour independently of the compensation lines

slope. Again, as expected, when the fixed variable is equal to their nominal value and the swept variable has the nominal value as well the frequency error is zero, see Fig. 4.11a and 4.11c. For each temperature there are different error values, the lowest temperature has always highest er-ror until the point they intercept when the temperatures invert, this behaviour is similar with the positive slope. −4 −2 0 2 4 −15 −10 −5 0 5 10 15 εV ctr (%) εf (%) T = −41°C T = −23°C T = −5°C T = 13°C T = 31°C T = 49°C T = 67°C T = 85°C T = 103°C T = 121°C (a) εVDD= 0% −4 −2 0 2 4 −5 0 5 10 15 20 25 εV ctr (%) εf (%) T = −41°C T = −23°C T = −5°C T = 13°C T = 31°C T = 49°C T = 67°C T = 85°C T = 103°C T = 121°C (b) εVDD= 2% −3 −2 −1 0 1 2 3 −15 −10 −5 0 5 10 15 εV DD (%) εf (%) T = −41°C T = −23°C T = −5°C T = 13°C T = 31°C T = 49°C T = 67°C T = 85°C T = 103°C T = 121°C (c) εVctr= 0% −3 −2 −1 0 1 2 3 −20 −15 −10 −5 0 5 10 15 εV DD (%) εf (%) T = −41°C T = −23°C T = −5°C T = 13°C T = 31°C T = 49°C T = 67°C T = 85°C T = 103°C T = 121°C (d) εVctr= 1%

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If VDD increases 2% of its nominal value then the Vctrhas to increase around 3 times to com-pensate the error, see Fig. 4.11b, on the other hand if Vctrincreases 1% then the VDDhas to increase around 0.75 times to compensate the error, see Fig. 4.11d. This clearly indicates that VDD has a stronger influence on the frequency deviation relatively to Vctrfor a deviation in percentage, show-ing a behaviour similar to the positive slope.

Fig. 4.12 clearly depicts the relation between VDD and Vctr for null frequency error, so it is

possible to identify how to vary the VDD or Vctr to compensate a given deviation of the other

voltage. Contrary to the positive slope, the relation between VDD and Vctr is not equal for any temperature, at ±1% can be seen already slightly different values. This analysis is very helpful to quantity how to compensate supply deviations on the RO control voltage which in this case have to be amplified on a linear manner throughout the temperature, the value in concrete is equal to slope of the plotted lines which varies around 2 for this oscillator.

−3 −2 −1 0 1 2 3 −4 −2 0 2 4 εV DD (%) εV ctr (%) T = −41°C T = −23°C T = −5°C T = 13°C T = 31°C T = 49°C T = 67°C T = 85°C T = 103°C T = 121°C

Figure 4.12: Null frequency error of simulated RO along temperature variation for typical process.

Fig. 4.13 takes into consideration another approach that is if the circuit compensating the RO varies the output (Vctr) proportionally to the supply voltage how would the oscillator behave in terms of frequency deviation. For example, for a deviation 1% on the supply voltage a maximum error close to 2.2% is obtained. A linear behaviour is observed for each temperature (straight lines), again being the lowest temperature that imposes the highest error, due to this linearity the weight has been quantified for the different temperatures by computing the slope of the straight lines in Fig. 4.13a. Fig. 4.13b depicts that slope which is around 1.5 times different between the

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36 CMOS Ring Oscillators −3 −2 −1 0 1 2 3 −8 −6 −4 −2 0 2 4 6 8 εV DD, εVctr (%) εf (%) T = −41°C T = −23°C T = −5°C T = 13°C T = 31°C T = 49°C T = 67°C T = 85°C T = 103°C T = 121°C

(a) Frequency error of εVDD= εVctr

0 50 100 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 Temperature ( °C) Slope (b) Slope of εVDD= εVctr

Figure 4.13: Frequency error and respective slope along temperature for typical process.

Again, due to the linearity observed in Fig. 4.11a and 4.11c, the frequency variations in relation to Vctrand VDDvariations (S

f

Vctr and S

f

VDD) are possible to be calculated using the equation 3.19.

Fig. 4.14a depicts S_Vf

ctr variation along temperature for different process corners which is a

good metric for error estimation and has been calculated for every RO within a good set of oscil-lators.

S_Vf

DD is shown in Fig. 4.14b with three different VDDvariations (1%, 3% and 5%) just to show

that for this slope the overlap of S_Vf

DD for different variations exists. S

f

VDD has a behaviour very

similar to the S_Vf_ctr just with a different absolute value, like with the positive slope.

0 50 100 20 25 30 35 40 45 50 55 Temperature ( °C) ∆ f / ∆ Vctr (KHz/mV) FF SF TT FS SS (a) S_Vf

ctrwith a fixed variation of 10mV around the nominal

Vctr(±5mV ). 0 50 100 20 25 30 35 40 45 Temperature ( °C) ∆ f / ∆ V DD (KHz/mV) FF ±1% variation SF ±1% variation TT ±1% variation FS ±1% variation SS ±1% variation FF ±3% variation SF ±3% variation TT ±3% variation FS ±3% variation SS ±3% variation FF ±5% variation SF ±5% variation TT ±5% variation FS ±5% variation SS ±5% variation (b) S_Vf

DDwith different variations around the nominal VDD

(2.8V ).

Figure 4.14: Frequency variation in relation to Vctrand VDDvariation along temperature for differ-ent process corners.

Process and Temperature Compensation of CMOS Ring Oscillators

F

E

U

P

Process and Temperature

Compensation of CMOS

Ring Oscillators

Henrique Manuel Dias Cavadas

Abstract

Resumo

Acknowledgements

Contents

List of Figures

List of Tables

List of Abbreviations

Chapter 1

Introduction

1.1

Problem Statement

1.2

Proposed Approach

1.3

Organization of this Dissertation

Chapter 2

Literature Review

2.1

Threshold Voltage (V

) Sensing

∑

2.2

Zero Temperature Coefficient (ZTC)

2.3

Wheatstone Bridge

Chapter 3

Characterization Techniques

3.1

Modified False-Position Algorithm

3.2

Coefficient of Determination

3.3

Matching lines

3.4

OAT Local Sensitivity Analysis

Chapter 4

CMOS Ring Oscillators

4.1

Single-Ended Current-Starved RO