Universidade de Aveiro Departamento de Eletrónica,Telecomunicações e Informática 2019
José Pedro
Oliveira Miranda
Amplificadores de Rádio Frequência Insensíveis à
Variação de Carga para Aplicações MIMO
Load Insensitive Radio Frequency Amplifiers to
MIMO applications
Universidade de Aveiro Departamento de Eletrónica,Telecomunicações e Informática 2019
José Pedro
Oliveira Miranda
Amplificadores de Rádio Frequência Insensíveis à
Variação de Carga para Aplicações MIMO
Load Insensitive Radio Frequency Amplifiers to
MIMO applications
Dissertação apresentada à Universidade de Aveiro para cumprimento dos re-quisitos necessários à obtenção do grau de Mestre em Engenharia Eletrónica e Telecomunicações, realizada sob a orientação científica do Doutor José Carlos Pedro, Professor Catedrático do Departamento de Eletrónica, Tele-comunicações e Informática da Universidade de Aveiro.
o júri / the jury
presidente / president Prof. Doutor José Rodrigues Ferreira da Rocha Professor Catedrático, Universidade de Aveiro
vogais / examiners committee Prof. Doutor Manuel Cândido Duarte dos Santos
Professor Auxiliar Convidado da Faculdade de Engenharia, Universidade do Porto
Prof. Doutor José Carlos Esteves Duarte Pedro Professor Catedrático, Universidade de Aveiro
agradecimentos /
acknowledgements todo o apoio, motivação e incentivo para a concretização deste projeto. EmAntes de mais, quero agradecer a um conjunto de pessoas que me deram primeiro lugar um especial agradecimento ao Professor Doutor José Carlos Pedro e ao meu colega de projeto Cristiano Gonçalves. Aos meus amigos, namorada e família que me acompanharam ao longo de todo este percurso. Por fim, um grande obrigado a todos os integrantes do Instituto de Telecomu-nicações por terem disponibilizado o espaço e todo o equipamento necessário para a concretização deste estudo.
Palavras Chave RFPA, Load Insensitive, Class-E, Efficiency, MIMO transmitter, 5G.
Resumo Esta dissertação aborda técnicas que mantenham a performance de um an-dar de amplificação RF, perante uma situação de variação de carga. Solu-ções como isoladores, amplificadores balanceados, antenas balanceadas e malhas de adaptação variáveis são abordadas do ponto de vista teórico. O amplificador em classe–E, em regime sub–ótimo provou ter um comporta-mento insensível à variação de carga. Este tipo de amplificador é conhecido pela sua elevada eficiência que, podendo ser combinada com a insensibi-lidade à variação de carga, pode afirmar-se como uma solução elegante e eficiente. Um transístor GaN HEMT de 10 W é usado como dispositivo ativo do amplificador e as malhas de adaptação impressas no substrato Isola Astra ( = 3 and h = 0.76). Com esta arquitectura foi obtida uma eficiência máxima de 74.3 %, com uma variação de 12.2 %, um ganho de 13.9 dB, com uma variação de 1.9 dB, para uma variação da resistência de carga compreendida entre 30 Ω e 200 Ω. Com estes resultados e segundo os parâmetros defini-dos neste documento, considerou-se um projecto insensível à resistência de carga.
Keywords RFPA, Load Insensitive, Class–E, Efficiency, MIMO transmitter, 5G.
Abstract This document focuses on techniques to make a radio frequency amplifying stage insensitive to load variation. Solutions like isolators, balanced ampli-fiers, balanced antenna and adaptive matching system are addressed from a theoretical point of view. The class–E working in sub-optimum regime has proved to maintain its efficiency over a certain load variation condition. This switching–mode class is known to achieve high efficiencies and combined with a load insensitive behaviour, can be definitely pointed as an elegant and simple solution. This configuration is implemented and tested. A 10W GaN HEMT transistor is the active device of the amplifier and the matching net-works printed in an Isola Astra substrate ( = 3 and h = 0.76). Attaining a maximum drain efficiency of 74.3 % with 12.2 % variation and 13.9 dB of max-imum gain with 1.9 dB variation, for a sweep of load resistances between 30 Ωand 200 Ω, the design is considered to be load insensitive according to the requirements of this dissertation.
Contents
Contents i
List of Figures iii
List of Tables v
Glossary vii
1 Introduction 1
1.1 Framework . . . 1
1.2 Framework and Objectives . . . 2
1.3 Document Structure . . . 3
2 Load-Insensitive RF Power Amplifiers 5 2.1 Definition of a Load Insensitive Power Amplifier . . . 5
2.2 Existing Solutions . . . 5
2.2.1 Isolators . . . 5
2.2.2 Balanced Amplifiers . . . 6
2.2.3 Balanced Antenna . . . 8
2.2.4 Adaptive Matching Systems . . . 8
3 Class E amplification 11 3.1 A brief introduction on switching mode amplification . . . 11
3.2 Class–E and possible variants . . . 11
3.2.1 Class E optimum operation regime . . . 12
3.2.2 Sub–optimum variable Slope Class E Power Amplifiers . . . 13
3.3 Resistive insensitive Class–E with an ideal switch . . . 14
3.3.1 Design equations . . . 14
3.3.2 Load network elements . . . 16
4 Resistance insensitive Class-E design and measurements 21
4.1 The active device and its DC characterization . . . 21
4.1.1 Transistor features and design considerations . . . 21
4.1.1.1 Estimating the transistor Ron and CDS . . . 21
4.1.2 I-V curves . . . 23
4.2 Bias Network . . . 23
4.3 Output Matching Network . . . 24
4.3.1 Implementing the RiCLE with microstrip lines . . . 26
4.3.2 Additional considerations . . . 29
4.4 Input Matching Network . . . 31
4.5 Layout and electromagnetic simulation . . . 33
4.6 Figures of merit and stability . . . 34
4.6.1 Simulation results . . . 34
4.6.2 Stability . . . 37
5 Experimental results and detailed analysis 39 5.1 Measurement setup and procedure . . . 39
5.2 Experimental results and analysis . . . 40
5.3 Observations . . . 43
6 Conclusions and Future Work 47
References 49
List of Figures
1.1 5G requirements [1] . . . 1
1.2 Two element multiple input multiple output (MIMO) transmitter with coupling effect . . 3
2.1 Amplifier and isolator. . . 6
2.2 Balanced Amplifier schematic. . . 6
2.3 Impedances for a mismatch condition - Red VSWR antenna; Blue VSWR Power Amplifiers (PAs). . . 7
2.4 Balanced Antenna schematic. . . 8
2.5 Adaptive Matching System - Closed Loop Technique. . . 9
3.1 Drain characteristics of an ideal transistor, with switching ON and OFF regions. . . 11
3.2 Class–E schematic with finite DC feed inductance. . . 12
3.3 Class–E, with finite DC feed inductance, drain and current waveforms. . . 14
3.4 The class–E design set K, in function of the parameter q [18]. . . . 15
3.5 Class–E circuit, for q = 1.3. . . . 17
3.6 Voltage (red) and current (blue) waveforms at switch. . . 17
3.7 . . . 18
3.8 Quasi–RFChoke and RiCLE efficiency for different load resistances . . . 18
4.1 CDS approximation . . . 23
4.2 Characteristic DC curve - IDS vs VDS (left); Characteristic DC curve - IDS vs VGS for VDS = 28V (right). . . 23
4.3 Bias circuit and impedances seen from the RF path. . . 24
4.4 Class-E circuit with Ron and CDS. . . 25
4.5 PA loads and switch efficiency. . . 25
4.6 Waveforms at the switch plane. . . 25
4.7 Tuned impedances at the intrinsic drain. . . 27
4.8 Time-domain waveforms at the intrinsic drain. . . 28
4.9 OMN schematic. . . 30
4.11 IMN schematic. . . 32
4.12 PA design. . . 33
4.13 Electrical simulated and electromagnetic simulated efficiencies versus Load Resistance. . . 35
4.14 Electrical simulated and electromagnetic gain versus Load Resistance. . . 35
4.15 Drain waveforms for different load resistance. . . 36
4.16 Stability circles from DC to 6 GHz. . . 37
4.17 Large signal analysis at 2GHz from -30 dBm to 30 dBm of input power. . . 38
5.1 Block diagram setup . . . 39
5.2 Load tuner measurements setup . . . 40
5.3 Measurements setup . . . 40
5.4 Electromagnetic simulated and experimental efficiency plots for each load resistance . . . 41
5.5 Electromagnetic simulated and experimental gain plots for each load resistance . . . 41
5.6 Transistor and Output Matching Network (OMN) characterized by their travelling waves amplitudes . . . 44
5.7 Efficiency plots calculated at different planes . . . 44 5.8 Losses between the intrinsic drain and the load: Int-Load ; Losses between the intrinsic
drain and the extrinsic: Int-Ext; Losses between the extrinsic drain and the load: Ext-Load 45
List of Tables
3.1 Circuit elements for a resistive–insensitive behaviour . . . 16
3.2 Fundamental impedances values . . . 17
3.3 Harmonic impedances values . . . 18
4.1 Transistor characteristics. . . 22
4.2 DC values. . . 23
4.3 Ideal and post-optimization impedances values. . . 26
4.4 Ideal and after optimization impedances values. . . 27
4.5 Ideal and adjusted conjugated gate impedances values. . . 31
4.6 Electric simulated and electromagnetic simulated efficiency values for each load resistance. 35 4.7 Electrical simulated and electromagnetic simulated gain values for each load resistance. . 36
5.1 Electromagnetic simulated and experimental efficiency values for each load resistance . . 41
5.2 Electromagnetic simulated and experimental gain values for each load resistance . . . 42
5.3 Efficiency values calculated at different planes . . . 44
5.4 Int - Losses between the intrinsic drain and the load ; Ext - Losses between the extrinsic drain and the load . . . 45
Glossary
4G forth generation
5G Fifth Generation of Mobile Networks
ADS Advanced Design System
CLEV S Class-E Variable Slope
CW Continuous Wave
DSP Digital Signal Processing
EM Electromagnetic
IMN Input Matching Network
IoT Internet of Things
LiPA Load Insensitive Power Amplifier
MEMS micro-electromechanical systems
MIMO multiple input multiple output
OMN Output Matching Network
PAE Power Added Efficiency
PAPR Peak-to-Average Power Ratios
PA Power Amplifier
PCB printed-circuit board
RAT radio access technologies
RFPA Radio Frequency Power Amplifier
RF Radio Frequency
RiCLE Resistance Insensitive Class-E
SC Smith Chart
SMD Surface Mount Device
VNA Vector Network Analyzer
VSWR Voltage Standing-Wave Ratio
ZSS Zero Slope Switching
1 | Introduction
1.1 FrameworkWireless communications play an important role in today’s society, being totally entrenched in our quotidian. Its contributions in the business sphere, medical care, entertainment, transportation, and so forth, had shortened distances interconnecting people and services all around the world. Mobile internet technology is currently evolving, driven by a combination of market demands and technology advances, each new generation brings new features that improve the experience for all users around the globe. The number of devices that claim wireless connection is dramatically increasing, and with it, arising different use cases and numerous applications demanding extreme capacity and performance.
Smart cities and smart houses are embedded in the Internet of Things (IoT) concept, where the interconnection and data transfer between cars, clothes, watches, body sensors, monuments and so forth, demand an ever-increasing bandwidth and system throughput, maintaining a low power consumption. This trend is expected to continue, which claim Fifth Generation of Mobile Networks (5G) systems to support much higher system capacity than current forth generation (4G), about 100 to 1000 times greater as illustrated in Figure 1.1 [1]. These highly demanding 5G design requirements claim a rethought on the entire network structure, undergoing the physical layer, software networks and network management. The target is not only to create new radio access technologies (RAT) and new standards but also integrating the existing technology to meet the requirements of 5G applications [2].
User experienced data rate (Mbit/s) 100 Spectrum efficiency 5G 3× 500 1 106 10 20 100× Mobility(km/h) Latency (ms) Connection density (devices/km2) Network energy efficiency Area traffic capacity (Mbit/s/m2)
Peak data rate (Gbit/s) 10 1× 400 350 10 105 10× 1× 1 0.1 1 4G Figure 1.1: 5G requirements [1]
The workhorse behind the implementation of 5G RAT relies on three main key approaches: Migrating the communication to higher frequencies, using MIMO transmitters and a density increase of radio resources, called the ultra-dense cell technology [1]. Fortunately, each individual approach presents a set of characteristics that enable a shared radio architecture. Higher the communication frequency, higher the miniaturization of the transmitter and receiver hardware chain, allowing a more condensed system. These characteristics that favours MIMO architecture. On the other hand, increasing the frequency of communication also means that the ratio between the received and transmitted power is smaller, due to an increase in the free space path losses. Here is where the MIMO directivity plays an important role. The capability of producing a narrow directional beam which can be oriented to a specific spatial area allows an efficient signal distribution over numerous low power, short range small cells. These concepts, combined with a proper Digital Signal Processing (DSP) algorithm allows a receiver/transmitter device to choose the best direction to establish a communication, avoiding obstructions, taking profit from multipath phenomena to strengthen the communication. Higher coverage area, enhance mobile broadband, low latency and reliable service to users are pointed at the main advantages of these symbioses.
1.2 Framework and Objectives
Figure 1.2 represents a MIMO system comprised of two transmitters A (blue) and B (red), where the coupling between antennas is marked in green. Each transmitter is composed by a power amplifier followed by a radiant element. The reflection coefficient seen by the power amplifier connected to the antenna A should be given by ρL= S11A and ρL= S22B for the one connected to antenna B. However, due to near field coupling phenomena between the antennas, the new coefficient seen by the power amplifier A is ρL= S11A+ S12ABb2B. Additionally, this change is dependent upon the beam focal direction, giving it a dynamic character. In sum, the PAs load depends upon the coupling between antennas of the array. Mismatch from the PA’s optimum load, affects its efficiency, degrading the overall performance of the MIMO system. This use case is where the necessity of a load insensitive power amplifier arises.
The main objectives of this dissertation are divided into two assignments. The first one is a research activity, focused on studying and investigating the existing technologies that enable a load insensitive behaviour. Whereas the second one relies on developing a Radio Frequency Power Amplifier (RFPA) prototype which maintains its efficiency under a certain load mismatch condition.
Figure 1.2: Two element MIMO transmitter with coupling effect
1.3 Document Structure
This document is structured as follows: Chapter 2 presents an overview of techniques that protect an amplifier stage under load mismatch, where are defined the characteristics that a PA should have to be considered load insensitive. Moreover, it is presented by existing solutions, discussing their advantages and drawbacks in today’s wireless systems. Chapter 3 briefly introduces the switching mode amplifiers, focusing on the class-E amplification. It is studied the optimum and sub-optimum operation regimes, are provided analytical expressions that ease their practical design. Additionally, it is introduced the resistive insensitive behaviour of a specific class-E amplifier, working on a sub-optimum regime. In chapter 4, the entire design methodology and simulation results are disseminated. Chapter 5 addresses the laboratory methodology, results and analysis of the attained experimental results, comparing with the ones presented in the simulation chapter. Lastly, chapter 6 presents the main difficulties and crucial points to be addressed in a Load Insensitive Power Amplifier (LiPA) design and the future work oriented to improve this circuit.
2 | Load-Insensitive RF Power
Amplifiers
2.1 Definition of a Load Insensitive Power Amplifier
Existing standards, or the upcoming ones, rely on high transmission rates and high directivity, making large-scale multi-antenna systems, for example, MIMO, an attractive method [3]. In perfect conditions, each antenna is matched to an amplifying stage. However, crosstalk due to mutual coupling changes the reflection coefficient seen by the amplifier, varying its load and consequently degrading its performance.
In handsets, preserving the PA’s performance under antenna impedance mismatch is a problem that becomes even harder to solve due to the lack of space available. Solutions using isolators, or other bulky components which enlarge the PA module, are more and more infeasible and must be rethought.
A PA is designed considering its load impedance to attain the desired output power and efficiency. The behaviour of the PA is highly dependent on the load impedance and it is sensitive to its variations. A PA is considered load insensitive if, once presented a certain range of load values around the optimum, the efficiency remains unaltered or with a small variation (up to 20% compared with its maximum).
The following chapter will briefly introduce the most commonly used solutions, addressing their advantages and drawbacks.
2.2 Existing Solutions 2.2.1 Isolators
A classical approach to prevent reflected waves from a mismatched antenna, flowing back to the amplifier, is using isolators. Distinguished by their non-reciprocal behaviour, the power transfer characteristics between ports 1 and 2, depends on where the signal is applied, being transmitted only in one direction (S21= 1) and absorbed in all the others (S11= 0; S12= 0; S22= 0) [4]. Ferrite is a non-reciprocal material and it is the most common element in isolators manufacturing at microwave frequencies [4]. Non-reciprocal materials are difficult to find in nature, which translates to high production costs. Besides this, isolators cannot be incorporated into IC technology due to their size.
Figure 2.1: Amplifier and isolator.
2.2.2 Balanced Amplifiers
Firstly introduced in 1965 [5], balanced amplifiers emerge as an alternative to isolators. Being more versatile and allowing on-chip integration, the benefits of this configuration were extensively accepted by the Radio Frequency (RF) community and completely refashioned the microwave amplifier industry by that time [6].
The balanced amplifier structure consists of two identical amplifier stages connected in parallel, with two quadrature couplers connected on both input and output ports, as pictured in Figure 2.2. The quadrature coupler exhibits a symmetry in its scattering matrix, meaning that, depending on the connection configuration, this device could behave as a power splitter or power combiner, as illustrated in Figure 2.2.
The isolator is placed between the amplifier and the antenna as showed in Figure 2.1.
Figure 2.2: Balanced Amplifier schematic.
Once the balanced amplifier is excited at port 1, the signal passes through the power splitter, producing two replicas with the same amplitude but half of the input power and in quadrature (90° out of phase). Hereafter, these replicas drive the branch PAs and are recombined by the second coupler. Due to the coupler phase characteristics, any mismatch at the input ports of the branch amplifiers is cancelled out at the input port of the balanced amplifier. The same happens for the balanced amplifier output port, providing a perfect match for the referred nodes [6].
Based on [7], the S parameters of the balanced amplifier are as given in equation 2.1.
S11= e−j∗π 2 ∗(S111− S112) S21= e−j∗π/2 2 ∗(S211− S212) S12= e−j∗π/2 2 ∗(S121− S12b) (2.1) S22= e−j∗π/2 2 ∗(S221− S222)
Performing a reciprocal analysis, if the antenna suffers from mismatch (ΓP ort2 6= 0), a reflected wave will travel towards the OMN of the branch amplifiers with half of the power. Due to the quadrature approach, both amplifiers experiment the same load mismatch in magnitude but with a phase difference of 180°.
In conclusion, if the antenna impedance varies within a certain Voltage Standing-Wave Ratio (VSWR) circle, the PAs see half of the VSWR variation respectively. In addition, the mismatched loads of both amplifiers are located precisely at opposite points from the Smith Chart (SC) centre, as pictured in Figure 2.3. The output power of one device will compensate the other at each phase angle, maintaining the balanced amplifier performance constant to load mismatch [8] [9].
Figure 2.3: Impedances for a mismatch condition - Red VSWR antenna; Blue VSWR PAs. The balanced amplifier architecture strongly relies on these principles to have optimum matching at its input and output ports. Nevertheless, this condition strongly depends on the degree of similarity of the branch amplifiers (S11 = S22= 0 if S111 = S112 and S221 = S222,
equation 2.1).
Although this solution is an improvement to the one previously mentioned, it still has some drawbacks. The balanced amplifier consumes more DC power and requires an extra
two quadrature modules and two amplifier stages, an implementation that occupies a larger on-chip area.
2.2.3 Balanced Antenna
Introduced by H. Heuermann [10], the balanced antenna brought the possibility of connecting a single-ended amplifier architecture into a Surface Mount Device (SMD) antenna structure. The coupler is designed to create a phase difference of -45° between ports 1 and 2 and 45° between ports 1 and 4.
Figure 2.4: Balanced Antenna schematic.
The amplifier is connected to port 1. A 50 Ohm load is connected to port 3 and two similar matched antennas are connected to ports 2 and 4. The power produced by the PA is evenly divided between the antennas. In the event of a mismatch, both antennas produce identical reflection coefficients. Therefore, a wave travelling to port 2 is reflected back and sums up a total phase difference of - 90° at port 1. In the same manner, a wave travelling to port 4 is reflected back, adding a total phase difference of 90° at the amplifier’s port. Now, both waves are 180° out of phase cancelling each other at the output of the PA. At port 3 the waves sum constructively, and the power is dissipated into the load.
This architecture seems pretty satisfactory in terms of performance, simplicity and on-chip requirements. However, the antennas have to be placed very close to each other so that the environmental conditions affect them equally, producing identical reflections at each dipoles [10]. Additionally, this configuration requires an extra module connecting the amplifier and the antenna, increasing the amount of space needed for this type of application.
2.2.4 Adaptive Matching Systems
In the following section, the adaptive matching system concept will be addressed in a black box approach, since there are numerous techniques to implement these solutions. The two most common approaches are the open loop and closed loop methods. The first utilises a lookup table, comprising system data measured apriori [11]. This method is the simplest but also the least accurate since it does not take into account the variations in components and in the environment. In contrast, the closed loop approach is continually measuring the antenna mismatch, adjusting the matching network accordingly. Hence, it is the most accurate and
commonly used approach. The adaptive matching system is placed between the amplifier and the antenna. It is essentially comprised of a mismatch detector, an adaptive matching network and a control unit, as presented in Figure 2.5.
Figure 2.5: Adaptive Matching System - Closed Loop Technique.
As seen in [11], [12], [13] and [14], there are plenty of techniques to detect the antenna mismatch, to implement the algorithm that adjusts the matching network and to develop the adaptive matching network. These techniques have a transversal workflow, presented here: (a) The mismatch detector identifies changes in the antenna reflection coefficient ΓL; (b) The control unit follows a specific algorithm to adjust the adaptive matching network so
that ΓAmigrates to a pre-established region of the Smith chart where the PA performance is preserved;
(c) The adaptive matching network is composed mainly by RF micro-electromechanical sys-tems (MEMS) capacitors, varactors and switches. These components provide adaptability to the network and are well known by their large tuning range [15], [16];
The discussed approach has demonstrated promising results, despite the increase of the system complexity. The different blocks needed to implement this technique are not trivial to replicate. The increase in complexity may prove to be harmful or simply not cost-efficient.
3 | Class E amplification
3.1 A brief introduction on switching mode amplificationThe necessity for highly efficient configurations, with high output powers, had opened a new horizon for the switching mode amplifiers. As can be observed in Figure 3.1, the transistor operates as a switch, commuting between the cut–off region (high resistance, off mode) and the triode region (low resistance, on mode). Thus, considering an ideal device - zero threshold voltage, zero on–resistance, infinite off resistance and instantaneous switching action - the voltage and current waveforms will have no overlap, achieving 100% of drain efficiency.
Figure 3.1: Drain characteristics of an ideal transistor, with switching ON and OFF regions.
3.2 Class–E and possible variants
Firstly introduced in [17], the class E configuration has been extensively studied and increas-ingly adopted in RF applications, mostly due to its high efficiency and simplicity. Presented in Figure 3.2, the class E circuit is composed by an inductor (L), a capacitor (C), a compensation element (X) and resonant circuit for harmonic suppression (L0, C0). Depending upon these circuit elements and input parameters - such as DC supply voltage, operation frequency, output power and duty–cycle - the class–E configuration can function in different regimes, as will be examined later. Although the initial circuit configuration was composed by a RF choke, instead of the finite DC feed inductor (L), the benefits of this change are well-known, enunciated in [18]:
• reduction in overall size and cost;
• reduction in supply voltage, which could enable this implementation in low supply voltages technologies;
• enabling larger switch capacitors (C) for the same supply voltage, output power and load. This enables higher operating frequencies;
The class–E circuit topology chosen, is composed by one shunt capacitor, a finite DC–feed inductance and a series reactance 3.2.
Figure 3.2: Class–E schematic with finite DC feed inductance.
The following sections have the aim to analyse the optimum and sub–optimum class–E operation regimes. To simplify the circuit analysis of each specific operation, it is common to make a number of widely accepted assumptions. These are presented below and enunciated in [19].
• the only real power loss in the circuit occurs on the load RL;
• the switch is loss-less, operating instantly with zero on–resistance and infinite off– resistance;
• the loaded quality factor (QL) of the series resonant circuit (L0 and C0) is high enough so that the output current is a sinusoidal wave at the switching frequency;
• the duty cycle is 50 %;
3.2.1 Class E optimum operation regime
Based on the class–E circuit pictured in Figure 3.2, ideally, when the transistor is conducting, there is no voltage across the capacitor and all the current flows into the transistor’s drain. When the device is cut off, the capacitor C creates a current path that forces a certain drain voltage. Power will be dissipated in the transistor’s drain whenever both current and voltage exists at that plane and at the same time. Therefore, it is crucial to guarantee that the capacitor is fully discharged at the turn–on moment.
Let us assume an angular frequency of ω, a duty–cycle of 50% and an input drive signal with a period of T = 2π
ω, where the switch is turned–on for the time interval of 0 ≤ t < π ω and turned–off for π
ω ≤ t <
2π
ω. For the optimum class–E operation, it is necessary to guarantee
the conditions 3.1 1 v(t)|t=2π ω = 0 dv(t) dt t=2π ω = 0 (3.1)
The first condition imposes Zero Voltage Switching (ZVS) at the turn–on instant, whereas the second imposes Zero Slope Switching (ZSS), meaning that the drain current is zero and has no oscillations, at that instant.
The circuit elements for the class–E optimum operation regime are calculated following the reasoning presented in [20], for a conduction angle of 180°, a VDD = 28V , a Pout= 10W and f = 2GHz. The simulator used is Advanced Design System (ADS). Figure 3.3a pictures the drain waveforms2.
3.2.2 Sub–optimum variable Slope Class E Power Amplifiers
Analysis such as [18], [19], [21] and [22], demonstrated that entering in the sub–optimum operation3 could bring some advantages relative to its precedent. In [19], analytical design equations are derived, streamlining the design of a Class-E Variable Slope (CLEV S). By selecting q = 1
ω√LC, certain load network elements are determined to implement the desired operation. This parameter is defined in [21] and determines how much the resonance frequency of the tank, created by the capacitor C and the DC–feed inductance L, deviates from the frequency of operation ω.
At switch turn–on moment, the CLEV S is described by the conditions 3.2, deducted in [19], for a duty–cycle of 50%. v(t)|t=2π ω = 0 dv(t) dt t=2π ω = ω.VDD.k (3.2)
The variable k is a real value that can be selected to obtain different behaviours of the drain waveforms, as described below.
• k = 0 is the classical class–E mode.
• k = −1.5 means that at switch turn–on instant, the current slope presents a negative value.
• k = 1.5 means that at switch turn–on instant, the current slope presents a positive value.
Depending on this variable, the drain waveforms are shaped as shown in Figure 3.3b.
1Based on the analysis made on [20].
2
The drain current and voltage equations are extensively derived in the literature. For the present simulation, the author followed [20].
3
(a) Optimum operation regime. 1 0 4 -1 2 3 I (t)/S I0 k=-1.5 k=0 k=1.5 V (t)/C VDD k=0 k=-1.5 k=1.5 time
(b) Sub–Optimum operation regime [19].
Figure 3.3: Class–E, with finite DC feed inductance, drain and current waveforms.
3.3 Resistive insensitive Class–E with an ideal switch
The modern modulation schemes have high Peak-to-Average Power Ratios (PAPR), meaning that the PA has to be efficient across a wide range of operating conditions [23]. The Doherty and outphasing architectures present an efficiency enhancement in back off power levels, relative to current mode designs. These implementations rely on controlling the load line of each PA branch adjusting its performance to the application needs, a process denominated by load modulation. Ideally, this modulation would correspond to move the load line of the PA along the real axis of the Smith chart. In other words, a pure load resistance variation, as it will be considered during this work.
In [24] the authors implemented a chirex–outphasing architecture with resistive insensitive class–E as branch amplifiers, where the harmonics were controlled inside the transistor’s package. The load variation presented to each PA is considered purely resistive, migrating from its optimum to a higher value. This work focus on realizing a similar branch amplifier in the same load variation conditions, resorting to a different technology and test bench. 3.3.1 Design equations
In the early days of class–E analysis, finding a direct relationship between input parameters (VDD, POU T, duty–cycle and ω) and the circuit element values (L, C, X and R) was not trivial and required a long, complex and iterative process. In [18], the authors derived simple design equations based on the class–E with finite DC feed inductance mathematical analysis. Assuming the use of an ideal switch, a sinusoidal output current on the load resistance and a 50% duty–cycle.
The design formulas given in Equation 3.3 are widely used in class–E designs, which relates the input parameters and the circuit element values. The authors express each element of the design set 3.3 in terms of q, originating infinitely many designs sets for the class–E PA. The curves plotted in Figure 3.4 result from the complex analytical analysis of those equations. The parameter q is defined in the entire interval except for the singular value q = 1.
KL(q) = ωL R KC(q) = ωCR KP(q) = POU TR V2 DD (3.3) KX(q) = X R
Figure 3.4: The class–E design set K, in function of the parameter q [18].
These functions were approximated by polynomials, performing a quadratic approximation. In Equation 3.4 is presented the design set for 0.6 < q < 1 and in Equation 3.5 is presented the design set for 1 < q < 1.65.
KL(q) = 44.93q2−94.32q + 52.46 KC(q) = 0.426q2−0.379q + 0.3 KP(q) = 0.74q2−0.6q + 0.76 (3.4) KX(q) = −0.73q2+ 0.411q + 1.03 KL(q) = 8.085q2−24.53q + 19.23 KC(q) = −6.97q3+ 25.93q2−31.07q + 12.48 KP(q) = −11.9q3+ 42.753q2−49.63q + 19.7 (3.5) KX(q) = −2.9q3+ 8.8q2−10.2q + 5.02
In conclusion, the work presented in [18] derived infinite class–E realizations, with straight-forward design equations. Appropriate circuit elements for a specific operation are determined, solely by setting the value of q. As an example, high values of KP(q) and KC(q) originate a high operation frequency and low supply voltage [18].
3.3.2 Load network elements
As mentioned above, the operation mode of a class–E power amplifier can be defined by the parameter q. Analysis such as [24], [23] and [25] suggests that, using a q ≈ 1.3, generates circuit elements that impose a resistive–insensitive behaviour.
Using the design Equations 3.5 for q = 1.3 and substituting in 3.3, is obtained the circuit elements shown in table 3.1, for POU T = 10W , f = 2GHz and VDD = 28V .
ROP T 101Ω
L 8.08nH
C 0.46pF LX 2.09nH
Table 3.1: Circuit elements for a resistive–insensitive behaviour
The harmonic filter should reject the harmonic frequencies bypassing the fundamental. It was designed for a QL= 100, using the Equations 3.6, presented in [18].
QL= ωL0 R ω = √ 1 L0C0 (3.6) 3.3.3 Validation
To validate this specific operation, a classical class–E topology with the circuit elements calculated above, is presented to an ideal switch, as pictured in Figure 3.5. The results are presented bellow, sweeping the load resistance from its optimum value R = ROP T to
R= ROP TX, where 1 < X < 5.
In this operation regime, once the load resistance migrates to higher values, the turn–on voltage remains zero but the voltage slope changes from zero to a negative value, entering in variable slope operation described by Equation 3.2. Thus, ideally, the overlap between the drain waveforms remains almost non–existent, preserving efficiency [24].
Using only lumped components in the network, real power losses only occur in the on– resistance of the switch. This parameter was set sufficiently small, being closer to an ideal switch. This means that efficiency losses are mainly due to the voltage and current waveforms overlap at the switch plane. It can be observed in Figure 3.7b, that for a quality factor of 100, the efficiency remains almost constant as the load resistance is increased from its optimum value. The loads presented to the transistor to attain this behaviour are presented in Figure 3.7a and its values in tables 3.2 and 3.3.
A second design followed the same analytical model but with its circuit elements calculated for q = 0.6, serves as a reference design to compare both operation regimes. This particular design tends to be an approximation of the classical class E RF Choke, described by Equations
Figure 3.5: Class–E circuit, for q = 1.3.
(a) RL= ROP T. (b) RL= ROP T∗ X.
Figure 3.6: Voltage (red) and current (blue) waveforms at switch.
X Impedances (Ω) 1 72.9 + j50.6 2 108.4 + j102.6 3 113.8 + j147.6 4 106.9 + j178.7 5 96.8 + j199.1
(a) Optimum impedances at the switching plane. (b) Efficiency versus load resistance plot for a QL= 100.
Figure 3.7
Frequency (GHz) Impedances (Ω)
4 0 + j147.1
6 0 + j69.6
Table 3.3: Harmonic impedances values
3.1. The parameter q is set to correspond with the highest DC feed inductance value covered by the design Equations 3.4 and 3.5. The efficiency versus load resistance of both Quasi–RFChoke and Resistance Insensitive Class-E (RiCLE) designs is pictured in Figure 3.8, where it is clear the resistive insensitive behaviour of the amplifier designed for q = 1.3. Moreover, in [24] is presented a similar analysis, where the parameter q is swept and still is the design obtained for q = 1.3, the one that is more insensitive to this load variation.
Figure 3.8: Quasi–RFChoke and RiCLE efficiency for different load resistances
In sum, this chapter establishes a connection between the design equations and the methodology to obtain the load network that implements a specific class–E operation, with resistive insensitive properties. It is relevant to refer that implementing this in a real transistor
is not as straightforward as in the ideal scenario, since the value of C is limited by the
CDS and the on–resistance of the transistor working in the triode region is not zero, being a characteristic property of the transistor’s technology. The next chapter will take into consideration the necessary modifications to the class–E design when the switch is replaced by a real transistor.
4 | Resistance insensitive Class-E
design and measurements
4.1 The active device and its DC characterization
This work was developed using an intrinsic model of the CGH40010F transistor from CREE, developed in IT Aveiro. A gallium nitride (GaN) high electron mobility transistor (HEMT), with 10W output power, suitable for RF applications. The substrate employed was Isola Astra (r= 3 and h = 0.76mm).
4.1.1 Transistor features and design considerations
The analysis of the time-varying voltage and current waveforms is useful to validate the intended class-E operation mode, for that reason, once implementing a switch mode amplifier, the access to the intrinsic model of the active device is of extreme utility. In this way, the drain waveforms exhibited by the transistor can be coherently compared with the ones attained in the ideal scenario, presented in the previous chapter.
Additionally, the designer should regard specific features inherent to the transistor technol-ogy and manufacture when choosing the active device. These significantly affect the Class-E performance, as stated by a brief description presented below:
Breakdown voltage (VBR) is the maximum drain-source voltage before the device disrup-tion. It is mandatory to assure that the drain voltage never exceeds this voltage. Its value can be consulted in the transistor’s datasheet, page 2;
On-state resistance (Ron) should be the minimum possible, since this will dissipate power when the transistor is conducting;
Off-state resistance should be the maximum possible, to avoid dissipated power when the transistor is cut-off;
Output capacitance (CDS) affects the switching action. The lower this value, the lower the charge and discharge time;
4.1.1.1 Estimating the transistor Ron and CDS
To implement this topology in a real transistor, the Ron value cannot be neglected, which implies that the assumptions made in Chapter 3 are no longer analytically exact, being solely an approximation. As an example, Equations 3.1 and 3.2 were derived assuming that the voltage across the capacitor (v(t)) is zero at the turn-off instant. This assumption is no
longer valid, since the on-resistance effect results in an overlap between the drain waveforms, dissipating power and further reducing the maximum efficiency achievable. Moreover, the switching is not instantaneous due to the parasitic capacitance CDS, becoming harder to fulfil the on and off switching requirements. The CDS imposes a lower limit to the optimum class-E shunt capacitance (C in Figure 3.5) calculated in the former chapter.
The ideal RiCLE network has to be tailored to the transistor’s parasitics. Following this reasoning, it is necessary to evaluate the on-resistance Ron and the CDS capacitance, readjusting the circuit pictured in Figure 3.5, to obtain the optimum loads that lead to a resistive insensitive behaviour on the real transistor.
The value of the on-resistance can be approximated by the inverse of the output conduc-tance, as shown in Equations 4.1 and 4.2.
gon= ∆I
∆V (4.1)
Ron= 1
gon (4.2)
where I/V relation in the triode region is approximated to:
gon= ∆IDSmax
− I0
∆V DSmax− VT H (4.3)
The value of the drain to source capacitance is imposed by the CDS and CGD non-linear capacitors, where the latter is reflected the output of the active device by Miller effect, as seen in Figure 4.1a.
CGDout =
CGD
1 − 1
Av
(4.4) The CCDout in Equation 4.4 represents the CGD capacitance reflected to the output of the amplifier. The Av represents the gate-to-drain voltage gain.
Since Av is much higher than 1, the Equation 4.4 can be re-written as Cout= CGD. These parasitics are voltage-dependent, demanding a DC drain-to-source voltage sweep to estimate the total CDS value. The schematic and the results obtained after this study can be observed in Figure 4.1a. The value of CDS capacitance obtained is given by the mean value of the curve pictured in Figure 4.1b.
The main transistors intrinsic characteristics results, studied in this section, can be consulted in table 4.1.
VBR (V) Ron (Ω) CDS (pF)
120 2.7 1.2
Table 4.1: Transistor characteristics.
(a) CGD and CDS projected using Miller effect
(b) Simulation for a varying VDS
Figure 4.1: CDS approximation
4.1.2 I-V curves
The transistor is biased near its threshold voltage, operating between the cut-off and triode regions. The drain voltage adopted was the one recommended by the manufacturer.
Figure 4.2 presents the DC characteristic curves for the mentioned transistor.
Figure 4.2: Characteristic DC curve - IDS vs VDS (left); Characteristic DC curve - IDS vs VGS for VDS = 28V (right).
VGS (V) VDS (V) IDS (mA)
-3.1 28 34
Table 4.2: DC values.
4.2 Bias Network
The bias network is designed to provide DC power to the transistor, filtering any RF signal that may reach the power supply or oscillations coming from it.
Two radial stubs were designed to short-circuit the fundamental and second harmonic frequencies, followed by a quarter wavelength transmission line. The latter transforms the low impedance seen by the central frequency to a high impedance assuring no power losses to the bias network. For the second harmonic, this line corresponds to a λ/2 rotation in the Smith chart, presenting a low impedance path to ground.
The reflection coefficient seen by the RF path is pictured in Figure 4.3b, for the fundamental, second harmonic frequencies and DC. The generic bias circuit used in this work is pictured in Figure 4.3a.
(a) Bias circuit. (b) Reflection coefficient.
Figure 4.3: Bias circuit and impedances seen from the RF path.
4.3 Output Matching Network
In a practical implementation, the circuit under study must represent an accurate approxima-tion of the transistor behaviour. Moreover, to estimate the desired output loads, the influence of the parasitic should be included and tailored regarding the transistor’s characteristics and technology. Such circuit is shown in Figure 4.4.
The circuit in Figure 3.5 was modified, adding the parasitic components calculated in 4.1. With the insertion of a resistive element Ron, power dissipation will occur at both the load resistance and the on-resistance, resulting in a peak efficiency drop. Additionally, since the transistor’s CDS is higher than the optimum capacitance derived by the equations, the load impedances which implement the intended behaviour will be shifted from the ideal scenario. As a consequence, the overlap between the drain waveforms increases dramatically, degrading the efficiency profile once the load resistance increases.
The circuit elements (L,X and RL) of the network were adjusted compensating the transistors parasitics, with the goal of reaching a similar efficiency performance pictured in Figure 4.5b and a similar waveform behaviour represented in Figure 4.6. At this phase, the author decided to extend the load ranges under study, testing the resistive insensitive behaviour for an interval comprehended between 30 Ω to 200 Ω. The new output loads to present to the intrinsic drain are pictured in Figure 4.5a, efficiency in Figure 4.5b and the intrinsic drain waveforms in Figure 4.6.
Figure 4.4: Class-E circuit with Ron and CDS.
(a) (b)
Figure 4.5: PA loads and switch efficiency.
(a) RL= 30 Ω. (b) RL= 50 Ω.
(c) RL= 200 Ω.
4.3.1 Implementing the RiCLE with microstrip lines
The ideal load network was derived above, using lumped components and an ideal switch. The transistor’s parasitics were estimated and included in the network, whose effects made necessary tuning of the remain circuit elements to obtain the intended resistive insensitive behaviour. The tuning was performed by tailoring the time domain voltage and current waveforms at the switch plane, following a practical waveform engineering strategy. The next step would focus on implementing this behaviour, substituting the switch by the transistor and the load network lumped components by microstrip lines, suitable for a practical RF implementation.
The harmonic impedances were the first to be matched. As the frequency increases, the physical length of the transmission line decreases. Therefore, it is a good practice to set the higher order harmonic frequencies near the transistor plane. Two capacitors were shunt connected to ground with their capacitance adjusted to filter the third and second harmonic frequency, respectively. By adjusting the lengths of the 3rdHarmonic and 2ndHarmonic lines in Figure 4.9, the harmonic impedances were properly set as depicted in Figure 4.7a. This methodology prevents the harmonic matching from being affected by the rest of the matching network. Although the bias network already cancels the second harmonic effect using a radial stub, the author decided to strengthen the short-circuit with a RF capacitor.
The most challenging goal of this design is to match the fundamental frequency over a wide range of load resistance while maintaining a simple and integrated layout. Hence, no parallel stubs were added to, performing the tuning routine simply by adjusting the length and width of the Fund line.
Figure 4.7b pictures the ideal impedances, obtained using the switch and lumped com-ponents represented in blue, and those obtained using the transistor and microstrip lines, represented in red.
The fundamental and harmonic matching was performed for a range of load resistances 30 Ω, 40 Ω, 50 Ω, 75 Ω, 100 Ω, 150 Ω and 200 Ω, and represents the impedances seen by the transistor’s intrinsic drain for each value load resistance. The values of the referred fundamental impedances are shown in table 4.5 and the harmonic impedances in Table 4.3
Frequency Ideal (Ω) After optimization (Ω) Second Harmonic 0.0 − j36.1 0.5 − j18.8
Third Harmonic 0.0 − j18.6 1.4 − 35.3 Table 4.3: Ideal and post-optimization impedances values.
(a) Harmonic impedances tuning method. (b) Ideal (blue) and impedances after tuning (red).
Figure 4.7: Tuned impedances at the intrinsic drain.
X Ideal (Ω) After optimization (Ω) 30 18.7 + j20.4 22.1 + j23.3 40 24.5 + j22.4 28.2 + j25.5 50 30.1 + j24.9 34.0 + j28.2 75 42.2 + j32.9 46.3 + j36.7 100 51.7 + j42.6 55.6 + j46.5 150 62.8 + j63.0 66.1 + j66.3 200 66.2 + j81.3 69.4 + 83.4
(a) RL= 50 Ω. (b) RL= 50 Ω.
(c) RL= 200 Ω.
Figure 4.8: Time-domain waveforms at the intrinsic drain.
4.3.2 Additional considerations
During the design, the author noticed that the power losses from the transistor’s drain to the load, increase for higher values of the load resistance. The last is defined in section 4.4 and arise from various factors, such as the transistor’s parasitics, series and shunt losses in the substrate and the series parasitic resistance of the capacitors. The total OMN losses versus load resistance profile is depicted in Figure 5.8. This phenomenon has to be taken into account once the objective is attaining a flat efficiency response, over the range of load resistance in the study. Therefore, it is of interest designing the PA to be more efficient for load resistances higher than the standard 50 Ω to compensate this drawback. The value of the DC block capacitor was carefully chosen to present a low impedance to the fundamental frequency, guaranteeing no losses at the operating frequency and shunt connected capacitors for the second and third harmonic frequencies.
Figure 4.9: OMN sc hematic. 30
4.4 Input Matching Network
Apart from providing DC power to the transistor and filtering low-frequency components, the Input Matching Network (IMN) should be designed to guarantee that the 50 Ω power source delivers the maximum power to the transistor’s gate. This is accomplished by performing a complex conjugate matching, where the IMN port that connects to the gate of the transistor presents the complex conjugate gate impedance, minimizing the reflected power between those points.
The class-E PA is a non-linear switching amplifier, being the greatest advantage of the high-efficiency throughput. The unbalance of the linearity-efficiency compromise makes high saturated measures a common practice for this type of PAs. This kind of measures is only possible in the laboratory if the device has sufficient power gain, for the entire range load resistances. The gain overload resistances is plotted in Figure 4.10a.
The IMN should include strategies to assure stability in small signal analysis for a large range of frequencies and in large signal simulation for the operating frequency. The RC filter is designed to control the low-frequency gain, and the 47 kΩ resistor prevents any feedback arising from the bias network. However, the design was unstable for frequencies near to its operating frequency. A common solution would be placing a resistor at the transistor’s gate, although it decreases the gain dramatically being harmful to the intended behaviour. The gain-stability compromise is reached by slightly increase the real part of the load presented by the IMN to the transistor’s gate. Figure 4.10a depicted that adjustment, in red the optimum gate complex-conjugate whereas in blue the adjusted IMN load.
(a) Gain versus Load Resistance.
(b) Impedance seen into the transistor’s gate.
Figure 4.10: Gain, Efficiency and PAE curves.
Ideal (Ω) adjusted (Ω) 2.7 − j0.1 7 + j0.4
Figure 4.11: IMN sc hematic. 32
4.5 Layout and electromagnetic simulation
The next step in this work relies on generating the PA layout and submitting the entire design to an electromagnetic simulation, which considers the coupling between microstrip lines, stubs and the ground plane. This coupling has impact on the matching, deviating the drain impedances from their optimum values, being necessary an a posteriori adjustment to meet the intended performance. Although it is important to provide proper spacing between conductive planes, it is also important that the PA overall dimensions remain reduced. Consequently, the
λ/4 line was meandered, which shortens the bias network and eliminates dead space in the
printed-circuit board (PCB). During this process, it is important to guarantee that the bias network maintains its performance.
The number of via holes1 and their distribution in the PCB is crucial to provide an equipotential ground plane. In the design given in Figure 4.12a, the author added a generous number of via holes near the shunt capacitors and the DC supply, maintaining a solid connection between the ground plane at the primary and secondary sides of the PCB. Additionally, the aluminium heatsink was designed to cover the entire surface of the PCB, guaranteeing a proper heat dispersion, with the screws forcing the contact between the transistor’s source and the ground plane.
Figure 4.12a represents the entire RiCLE layout, where the circles with the largest radius represent the screws that attach the PCB to the aluminium base. The remaining ones represent the vias holes.
Figure 4.12b shows the entire PA after attaching the transistor, soldering all components and the wires for the DC supply.
(a) Complete layout. (b) Practical implementation.
Figure 4.12: PA design.
4.6 Figures of merit and stability 4.6.1 Simulation results
The following section compares the efficiency and gains over the entire range of load resistances, of both the electric and electromagnetic simulations. The efficiency values are calculated dividing the root mean square complex power at the load plane, by the DC power dissipation.
Ef f =
1
2 · Real(vout· iout)
VDC· IDC (4.5)
The gain is attained by subtracting the input power to the rms complex power at the load plane.
Gain= 1
2· Real(vout· iout) − Pin (4.6) The efficiency values presented were obtained with an output power measured at a 3 dB gain compression. It can be observed in Figure 4.13 that the peak efficiency is achieved at the 50 Ω load resistance at both simulation environments. This deviation from the intended efficiency curve obtained with an ideal switch and lumped components, presented in Figure 4.5b, is justified by the divergence of the ideal loads and the ones attained with microstrip lines and the actual transistor. In Figure 4.7b this imprecision is clearly reflected, where the actual impedances suffered a right shift relative to the ideal ones, making the optimum load in terms of efficiency the 50 Ω instead of the 100 Ω.
In Figure 4.13, it is also detected a decrease in efficiency for the entire range of load resistances when comparing the electric simulation and the electromagnetic simulation, which can be justified by the electromagnetic coupling between the passive components. This coupling cause imprecision in the matching process and contributes to further power losses, which reduce the efficiency for the entire range of load resistances.
The gain versus load resistances present a quasi-flat profile, that is mandatory for this type of design. The slight increase in the electromagnetic simulation relative to the electric one can be justified by a deviation of the real part of the IMN optimum load. After this divergence, the amplifier stability was once again confirmed.
By examining the drain waveforms exhibited in Figure 4.15b, it can be noticed that the switching action is not instantaneous, manifesting an overlap at the on and off instants. This overlap is mirrored in a decrease of efficiency relative to the ideal design. The drain waveform’s lag increases as the load resistance are changed from its optimum value, as can be observed in Figures 4.15a and 4.15c. Furthermore, the efficiency drops for the highest load resistance value, a behaviour that will be carefully analysed and justified in the following chapter.
These waveforms were obtained in the electromagnetic simulation and are similar to the ones obtained in the electric simulation.
Figure 4.13: Electrical simulated and electromagnetic simulated efficiencies versus Load Resistance.
Load
Resistance (Ω) Electrical simulationefficiency (%) Electromagnetic simulationefficiency (%)
30 68.6 62.4 40 73.7 70.0 50 74.8 72.9 75 74.3 72.7 100 72.5 71.1 150 67.6 66.4 200 62.8 61.7
Table 4.6: Electric simulated and electromagnetic simulated efficiency values for each load resistance.
Load
Resistance (Ω) Electrical simulationgain (dB) Electromagnetic simulationgain (dB)
30 13.0 13.4 40 13.6 14.0 50 14.0 14.4 75 14.3 14.8 100 14.4 14.9 150 14.2 14.7 200 13.8 14.4
Table 4.7: Electrical simulated and electromagnetic simulated gain values for each load resistance.
(a) RL= 30 Ω. (b) RL= 50 Ω.
(c) RL= 200 Ω.
Figure 4.15: Drain waveforms for different load resistance.
4.6.2 Stability
The effect of various load resistances presented to the amplifier’s output demand a particular stability analysis. It is necessary to guarantee that the entire range of load resistances could be connected to the PA without generating an unstable design.
ADS has stability analysis tool that generates the load and source stability contours and determines the stable zone, making this analysis fast and straightforward.
In the first stage, the amplifier was submitted to a small signal analysis from DC up to 4 GHz. For each frequency, the author guaranteed that all load resistances were in the stable zone of the load stability circles. In Figure 4.16b the blue dot corresponds to the 30 Ω impedance and the pink dot corresponds to the 200 Ω impedance. Following the same methodology, it is verified that a 50 Ω source can be attached to the PA’s input, Figure 4.16a.
Since the amplifier is tested with high input powers, the previous analysis does not guarantee a stable design under those circumstances. Therefore the PA was submitted to a large signal simulation, from a range of input powers from -30 dBm up to 35 dBm. Again, all the load resistances were inside the stable zone of the load stability circles, presented in Figure 4.17b, where the blue dot corresponds to the 30 Ω impedance and the pink dot corresponds to the 200 Ω impedance. The same is verified for the 50 Ω source, analogously to the small signal analysis.
The following stability circles were obtained in the electromagnetic simulation and are similar to the ones obtained in the ADS one.
(a) Source stability circles. (b) Load stability circles.
(a) Source stability circles. (b) Load stability circles.
Figure 4.17: Large signal analysis at 2GHz from -30 dBm to 30 dBm of input power.
5 | Experimental results and
detailed analysis
5.1 Measurement setup and procedure
The laboratory apparatus used to test the behaviour of the RiCLE PA is depicted in Figure 5.1, in the form of a block diagram. The device is tested with a Continuous Wave (CW), with a fixed frequency 2 GHz at its input. A trial consists of sweeping the input power of the driving signal for one specific load resistance. There were performed 7 trials for each load resistance under study, where both the output power and DC power were measured.
Figure 5.1: Block diagram setup
One of the challenges of testing such a circuit is to emulate the impedances used during the simulation. With that purpose, the author resourced to the system depicted in Figure 5.2, where a Vector Network Analyzer (VNA) displays the impedance set by the mechanical load tuner, with the attenuators load effect. By a trial and error process, the stubs of the load tuner were adjusted, until fixing the intended load impedance. For the calibration between the stub length and the impedance, a calliper is used with an accuracy of 0.02 mm.
The whole PA measurement setup can be observed in picture 5.3. In the first stage, the transistor was biased starting in a deep cut-off condition. The gate voltage was slowly increased until attaining the intended bias drain current (34 mA).
During the main test, the CW generator drives the circuit with a 2 GHz signal, sweeping the wave amplitude. For each load resistance exhibited by the load tuner, the output power is measured using the power meter. The results are presented in the next section.
Figure 5.2: Load tuner measurements setup
Figure 5.3: Measurements setup
5.2 Experimental results and analysis
For the optimum resistance, the PA exhibited the maximum measured efficiency of 74.3 % at 3 dB gain compression. For the highest value of the load resistance the PA presents an efficiency of 62.1%, exhibiting a difference of 12.2 % comparing with its maximum value, as can be confirmed in table 5.1. Regarding the definition enunciated in chapter 2 the amplifier can be considered resistive insensitive for the output loads comprehended between 30 Ω and 200 Ω, where only presents a decrease of 12.2% relative to the maximum value of efficiency.
The gain decreased by 1.9 dB on average, relative to the results obtained in the Electromagnetic (EM) simulation. This deviation can be assigned to a small error in the IMN manufacturing. Nevertheless, this difference is not relevant since the amplifier presents a decent gain, allowing measurements at 3 dB gain compression for the whole range of load resistances.
Figure 5.4: Electromagnetic simulated and experimental efficiency plots for each load resistance
Load
Resistance (Ω) Electromagnetic simulationefficiency (%) efficiency (%)Measured
30 62.4 63.8 40 70.0 69.5 50 72.9 71.7 75 72.7 73.6 100 71.1 74.3 150 66.4 71.9 200 61.7 62.1
Table 5.1: Electromagnetic simulated and experimental efficiency values for each load resistance
Load
Resistance (Ω) EM simulationgain (dB) gain (dB)Measured
30 13.4 12.7 40 14.0 13.2 50 14.4 13.4 75 14.8 13.9 100 14.9 14.2 150 14.7 14.0 200 14.4 14.3
Table 5.2: Electromagnetic simulated and experimental gain values for each load resistance
5.3 Observations
By examining Figure 5.6, to guarantee that the maximum power available from the transistor is delivered to the OMN, the network has to present no losses, i.e. PN ET = PLOAD. The transistor’s parasitics and substrate series and shunt losses, dissipate power and further reduce the efficiency.
The losses in the OMN can be derived in function of the power entering in this network (PN ET at port 1) and the power that is leaving (PLOAD at port 2). These powers can be expressed in terms of its travelling waves amplitudes as:
PN ET = 12(|a1|2− |b21|) (5.1) PLOAD= 1 2(|b2|2− |a22|) (5.2) where, b1 = S11a1+ S12a2 (5.3) b2 = S21a1+ S22a2 (5.4)
By definition, the reflected travelling waves (b1 and a2) can be written as function of their respective reflection coefficients by:
b1= ΓN ET · a1 (5.5) a2 = ΓLOAD· b2 (5.6) Replacing 5.4 in 5.4: b2 a1 = S21 1 − S22·ΓLOAD (5.7)
Finally, the losses in the OMN are given by the following ratio:
PLOAD PN ET = 1 1 − |ΓN ET|2 · |S21| · 1 − |ΓLOAD| 2 |1 − S22·ΓLOAD|2 (5.8) Gain and efficiency were calculated using the power measured at three different planes of the PA - at the intrinsic and extrinsic drain and at the load (Figure 5.6). The intrinsic measurements are calculated with the available power to be delivered to the load resistance (PN ET). In the extrinsic measurements are reflected the losses due to the transistor’s parasitics. Whereas the load measurements include all the losses between the transistor’s output and the load resistance, computed with PLOAD.
These values were computed after the EM simulation for the same input power requirements presented. By analysing Figure 5.7, it is verified that could have been possible to achieve
higher efficiencies values, for the design. As an example, for the 50 Ω load resistance the losses between the intrinsic drain and the load are of 0.47 dB (table 5.4) which traduces in an 8.4 % decrease in efficiency relative to the ideal scenario. To improve this design, the design of the OMN must be further optimized, reducing its size, using better substrates and even exploring new techniques like adaptive matching networks.
Figure 5.6: Transistor and OMN characterized by their travelling waves amplitudes
Figure 5.7: Efficiency plots calculated at different planes
Load
Resistance (Ω) drain efficiency (%)Intrinsic drain efficiency (%)Extrinsic efficiency (%)Load
30 70.9 66.8 62.4 40 78.5 74.4 70.0 50 81.3 77.4 72.9 75 81.1 77.4 72.7 100 80.0 76.4 71.1 150 76.7 72.9 66.4 200 73.4 69.4 61.8
Table 5.3: Efficiency values calculated at different planes
Figure 5.8: Losses between the intrinsic drain and the load: Int-Load ; Losses between the intrinsic drain and the extrinsic: Int-Ext; Losses between the extrinsic drain and the load: Ext-Load
Load
Resistance (Ω) Int-Load (dB) Int-Ext (dB) Ext-Load (dB)
30 0.55 0.26 0.29 40 0.49 0.23 0.26 50 0.47 0.21 0.25 75 0.47 0.19 0.27 100 0.51 0.20 0.31 150 0.62 0.21 0.40 200 0.75 0.24 0.50
Table 5.4: Int - Losses between the intrinsic drain and the load ; Ext - Losses between the extrinsic drain and the load
