Lecture 4: DC & Transient Response

Introduction to CMOS VLSI

Design

Lecture 4:

DC & Transient Response

Greco/Cin-UFPE

(Material taken/adapted from Harris’ lecture notes)

Outline

 DC Response

 Logic Levels and Noise Margins

 Transient Response

 Delay Estimation

Activity

1)     If the width of a transistor increases, the current will increase decrease not change

2)     If the length of a transistor increases, the current will increase decrease not change

3)     If the supply voltage of a chip increases, the maximum transistor current will

increase decrease not change

4)     If the width of a transistor increases, its gate capacitance will increase decrease not change

5)     If the length of a transistor increases, its gate capacitance will increase decrease not change

6)     If the supply voltage of a chip increases, the gate capacitance of each transistor will

increase decrease not change

Activity

1)     If the width of a transistor increases, the current will increase decrease not change

2)     If the length of a transistor increases, the current will increase decrease not change

3)     If the supply voltage of a chip increases, the maximum transistor current will

increase decrease not change

4)     If the width of a transistor increases, its gate capacitance will increase decrease not change

5)     If the length of a transistor increases, its gate capacitance will increase decrease not change

6)     If the supply voltage of a chip increases, the gate capacitance

DC Response

 DC Response: V_out vs. V_in for a gate

 Ex: Inverter

– When V_in = 0 -> V_out = V_DD – When V_in = V_DD -> V_out = 0 – In between, V_out depends on

transistor size and current

– By KCL, must settle such that I_dsn = |I_dsp|

– We could solve equations

– But graphical solution gives more insight

I_dsn I_dsp

V_out V_DD

V_in

Transistor Operation

 Current depends on region of transistor behavior

 For what V_in and V_out are nMOS and pMOS in – Cutoff?

– Linear?

– Saturation?

nMOS Operation

Cutoff Linear Saturated

V_gsn < V_gsn >

V_dsn <

V_gsn >

V_dsn >

I_dsn I_dsp

V_out V_DD

V_in

nMOS Operation

Cutoff Linear Saturated

V_gsn < V_tn V_gsn > V_tn

V_dsn < V_gsn – V_tn

V_gsn > V_tn

V_dsn > V_gsn – V_tn

I_dsp

V_out V_DD

V_in

nMOS Operation

Cutoff Linear Saturated

V_gsn < V_tn V_gsn > V_tn

V_dsn < V_gsn – V_tn

V_gsn > V_tn

V_dsn > V_gsn – V_tn

I_dsn I_dsp

V_out V_DD

V_in

V_gsn = V_in V_dsn = V_out

nMOS Operation

Cutoff Linear Saturated

V_gsn < V_tn V_in < V_tn

V_gsn > V_tn V_in > V_tn

V_dsn < V_gsn – V_tn V_out < V_in - V_tn

V_gsn > V_tn V_in > V_tn

V_dsn > V_gsn – V_tn V_out > V_in - V_tn

I_dsp

V_out V_DD

V_in

V_gsn = V_in V = V

pMOS Operation

Cutoff Linear Saturated

V_gsp > V_gsp <

V_dsp >

V_gsp <

V_dsp <

I_dsn I_dsp

V_out V_DD

V_in

pMOS Operation

Cutoff Linear Saturated

V_gsp > V_tp V_gsp < V_tp

V_dsp > V_gsp – V_tp

V_gsp < V_tp

V_dsp < V_gsp – V_tp

I_dsp

V_out V_DD

V_in

pMOS Operation

Cutoff Linear Saturated

V_gsp > V_tp V_gsp < V_tp

V_dsp > V_gsp – V_tp

V_gsp < V_tp

V_dsp < V_gsp – V_tp

I_dsn I_dsp

V_out V_DD

V_in

V_gsp = V_in ^{- V}_DD V_dsp = V_out - V_DD

V_tp < 0

pMOS Operation

Cutoff Linear Saturated

V_gsp > V_tp

V_in > V_DD + V_tp

V_gsp < V_tp

V_in < V_DD + V_tp V_dsp > V_gsp – V_tp V_out > V_in - V_tp

V_gsp < V_tp

V_in < V_DD + V_tp V_dsp < V_gsp – V_tp V_out < V_in - V_tp

I_dsp

V_out V_DD

V_in

V_gsp = V_in ^{- V}_DD V = V

V_tp < 0

I-V Characteristics

 Make pMOS is wider than nMOS such that _n = _p

V_gsn5

V_gsn4 V_gsn3 V_gsn2 V_gsn1

V_gsp5 V_gsp4 V_gsp3 V_gsp2 V_gsp1

V_DD -V_DD

V_dsn -V_dsp

-I_dsp I_dsn

0

Current vs. V

, V

V_in5

V_in4

V_in3 V_in2 V_in1 V_in0

V_in1

V_in2 V_in3 V_in4 I_dsn, |I_dsp|

Load Line Analysis

V_in5

V_in4

V_in3 V_in2 V_in1 V_in0

V_in1

V_in2 V_in3 V_in4 I_dsn, |I_dsp|

V_out V_DD

 For a given V_in:

– Plot I_dsn, I_dsp vs. V_out

– Vout must be where |currents| are equal in

I_dsn I_dsp

V_out V_DD

V_in

Load Line Analysis

V_in0 V_in0

I_dsn, |I_dsp|

 V_in = 0

Load Line Analysis

V_in1 V_in1

I_dsn, |I_dsp|

V_out V_DD

 V_in = 0.2V_DD

Load Line Analysis

V_in2 V_in2

I_dsn, |I_dsp|

 V_in = 0.4V_DD

Load Line Analysis

V_in3 V_in3

I_dsn, |I_dsp|

V_out V_DD

 V_in = 0.6V_DD

Load Line Analysis

V_in4

V_in4 I_dsn, |I_dsp|

 V_in = 0.8V_DD

Load Line Analysis

V_in5 V_in0

V_in1

V_in2 V_in3 V_in4 I_dsn, |I_dsp|

V_out V_DD

 V_in = V_DD

Load Line Summary

V_in5

V_in4

V_in3 V_in2 V_in1 V_in0

V_in1

V_in2 V_in3 V_in4 I_dsn, |I_dsp|

DC Transfer Curve

 Transcribe points onto V_in vs. V_out plot

V_in5

V_in4

V_in3 V_in2 V_in1 V_in0

V_in1

V_in2 V_in3 V_in4

V_out V_DD

C V_out

0

V_in

V_DD V_DD

A B

D E

V_tn V_DD/2 V_DD+V_tp

Operating Regions

 Revisit transistor operating regions

C V_out

0

V

V_DD V_DD

A B

D E

V_tn V_DD/2 V_DD+V_tp

Region nMOS pMOS A

B C D E

Operating Regions

 Revisit transistor operating regions

C V_out

0

V_in

V_DD V_DD

A B

D E

V_tn V_DD/2 V_DD+V_tp

Region nMOS pMOS

A Cutoff Linear

B Saturation Linear

C Saturation Saturation

D Linear Saturation

E Linear Cutoff

Beta Ratio

 If _p / _n  1, switching point will move from V_DD/2

 Called skewed gate

 Other gates: collapse into equivalent inverter

V_out

0 V_DD

0.5 21

p 10

n



 ^

p 0.1

n



 ^

Noise Margins

 How much noise can a gate input see before it does not recognize the input?

Indeterminate Region NM_L

NM_H

Input Characteristics Output Characteristics

V_OH V_DD

V_OL

GND V_IH

V_IL

Logical High Input Range

Logical Low Input Range Logical High

Output Range

Logical Low Output Range

 By definition, V_IH and V_IL are the operational points of the inverter where

V_out

V_OH

V_DD Unity Gain Points

Slope = -1

_p/_n > 1 V_in V_out

A high gain (g) is desirable

Logic Levels

 To maximize noise margins, select logic levels at

V_DD V_in V_out

V_DD

_p/_n > 1 V_in V_out

0

Logic Levels

 To maximize noise margins, select logic levels at – unity gain point of DC transfer characteristic

V_out

V_OH

V_DD Unity Gain Points

Slope = -1

_p/_n > 1 V_in V_out

Transient Response

 DC analysis tells us V_out if V_in is constant

 Transient analysis tells us V_out(t) if V_in(t) changes – Requires solving differential equations

 Input is usually considered to be a step or ramp – From 0 to V_DD or vice versa

Inverter Step Response

 Ex: find step response of inverter driving load cap

(

)

(

) )

(

o i

ut n

out

V t t t

V t V

d d

t



 



V_in(t)

V_out(t) C_load I_dsn(t)

Inverter Step Response

 Ex: find step response of inverter driving load cap

0 0

( )

( )

( )

( )

ou

DD in

t out

u t t V

d d

t

t t V t V

V

t











V_in(t)

V_out(t) C_load I_dsn(t)

Inverter Step Response

 Ex: find step response of inverter driving load cap

0

(

( )

) ( (

) )

DD D

o i

D o t

n

ut u

V t

u t t V V

d d

t

t V

V

t t

 







V_in(t)

V_out(t) C_load I_dsn(t)

Inverter Step Response

 Ex: find step response of inverter driving load cap

0

0

( )

( )

( ) (

(

) )

DD DD

loa d ou

i

d t

o n

ut sn

V V

u t t V t t

V t

V d

dt C

t

I t

 



 



0

( ) _{out DD t}

ou ds

t DD t

I n t V V

V

V V

V

t t



   

  



V_in(t)

V_out(t) C_load I_dsn(t)

Inverter Step Response

 Ex: find step response of inverter driving load cap

0

0

( )

( )

( ) (

(

) )

DD DD

loa d ou

i

d t

o n

ut sn

V V

u t t V t t

V t

V d

dt C

t

I t

 



 



 

0 2

2

0 )

( _{DD out DD t}

n

Ids V

t t

V V V V

t ^

 



    

V_in(t)

V_out(t) C_load I_dsn(t)

Inverter Step Response

 Ex: find step response of inverter driving load cap

0

0

( )

( )

( ) (

(

) )

DD DD

loa d ou

i

d t

o n

ut sn

V V

u t t V t t

V t

V d

dt C

t

I t

 



 



 

0 2

2

0

)2 )

( ( )

( _{DD DD t}

DD

out

out out out D t

n

t ds

D

I V

t t

V V V V

V V V V V

t

V t V t





 



    

      

  



V_out(t) V_in(t)

t₀ t

V_in(t)

V_out(t) C_load I_dsn(t)

nMOS – “1” transfer is bad

Delay Definitions

 t_pdr: rising propagation delay

– From input to rising output crossing VDD/2 (upper bound)

 t_pdf: falling propagation delay

– From input to falling output crossing VDD/2 (upper bound)

 t_pd: average propagation delay – t_pd = (t_pdr + t_pdf)/2

 tr: rise time

– time required for a node to charge from the 10% point to 90% ( 0.1 V_DD to 0.9 V_DD )

 t_f: fall time

T_{pdr =} T_pHL T_{cdf =} T_pHL

t_r t_f

Delay Definitions

CMOS Inverter Switching Characteristics

 Define:

– Falling delay t_df = delay time with output falling – Rising delay t_dr = delay time with output rising

Trajectory of a n-transistor operating point

a. Transistor is Cut off

a. Applying a V_gs=V_DD b. V_out -> 0,9 to (V_DD-T_th) a. V_DD-T_th -> to 0.1V

Fall-time equivalent circuit

Rise-time equivalent circuit

The fall-time is faster than the rise time,

t_f=t_r/2

primarily due to different carrier mobilities associated with the p and n- devices:

µ_n = 2 µ_p

 If the designer wants to have both n an p transistor with the same rise and fall time:

β_n / β_p = 1

 This implies that channel width for the p-device must be increased to approximately two to three times of the n-device:

w_p = 2 – 3 w_n

n+ n+

p-type body

W

L t_ox

SiO₂ gate oxide (good insulator, _ox = 3.9₀) polysilicon

gate

Trajectory of a n-transistor operating

point

Delay Estimation

 We would like to be able to easily estimate delay – Not as accurate as simulation

– But easier to ask “What if?”

 The step response usually looks like a 1^st order RC response with a decaying exponential.

 Use RC delay models to estimate delay – C = total capacitance on output node – Use effective resistance R

– So that t_pd = RC

 Characterize transistors by finding their effective R

RC Delay Models

 Use equivalent circuits for MOS transistors

– Ideal switch + capacitance and ON resistance – Unit nMOS has resistance R, capacitance C – Unit pMOS has resistance 2R, capacitance C

 Capacitance proportional to width

 Resistance inversely proportional to width

k g

s d

g

s d

kC kC

R/k kC

k g

s d

g

s

d kC

kC kC 2R/k

Capacitance

proportional to width

Resistance inversely

proportional to width

nMOS pMOS

 Resistance of a uniform slab:

– R =  (l/A) = (/t) (L/W) where  is the resistivity in ohm-cm, t is the thickness in cm, L is the length, W is the width, and A is the cross-sectional area

– Using the concept of sheet resistance, R = R_s (L/W) where R_s is called the sheet resistance and given in ohms per square

• Rs =  / t

 Gate Capacitance -

C_g = _oxWL/t_ox  = _oxA/t_ox 

n+ n+

p-type body

W

L t_ox

SiO₂ gate oxide (good insulator, _ox = 3.9₀) polysilicon

gate

RC Delay Models

MOS device capacitances

 MOS Device capacitances

– Cgs, C_gd = gate-to-channel capacitances, which are lumped at the source and the drain regions.

– Csb, Cdb = source and drain-duiffusion capacitances to bulk (or substrate) – Cgb = gate –to-bulk capacitance

1. Off region, where V_{gs <} V_t. There is no channel C_gs, C_gd = 0.

2. Non-saturated region, where V_gs - V_t. > V_ds. C_gb = 0

3. Saturated region, where V_{gs <-}V_t. < V_ds. Channel is heavely inverted.

The drain is pinched off causing C_gd = 0.

MOS device capacitances

RC Delay Models

pMOS capacitance

= 2x nMOS capacitance

Example: 3-input NAND

 Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

Example: 3-input NAND

 Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

Example: 3-input NAND

 Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

3 3 2 2

2

3

3-input NAND Caps

 Annotate the 3-input NAND gate with gate and diffusion capacitance.

2 2 2

3 3 3

3-input NAND Caps

 Annotate the 3-input NAND gate with gate and diffusion capacitance.

2 2 2

3 3

3 3C

3C 3C 2C

2C

2C 2C

2C 2C

3C 3C

2C 2C 2C

Resultant capacitance per gate = 2C+3C = 5C

Parallel capacitances 3x2C+3C = 9C

3-input NAND Caps

 Annotate the 3-input NAND gate with gate and diffusion capacitance.

9C 3C 3 3C

3 3 2 2

2 5C

5C

5C

Elmore Delay

 ON transistors look like resistors

 Pullup or pulldown network modeled as RC ladder

 Elmore delay of RC ladder

R₁ R₂ R₃ R_N

C C C C

   

nodes 

1 1 1 2 2

...

...

pd i to source i

i

N N

t R C

R C R R C R R R C



       



Example: 2-input NAND

 Estimate worst-case rising and falling delay of 2- input NAND driving h identical gates.

h copies

2 2 2 2

B A

x

Y

Example: 2-input NAND

 Estimate worst-case rising and falling delay of 2- input NAND driving h identical gates.

h copies

Example: 2-input NAND

 Estimate worst-case rising and falling delay of 2- input NAND driving h identical gates.

h copies

Parallel capacitances 2C+2C+2C= 6C

Example: 2-input NAND

 Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates.

h copies

6C 2 2C

2 2 2

4hC B

A

x

Y

Example: 2-input NAND

 Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates.

h copies

6C 2 2C

2 2 2

4hC B

A

x

Y

R

(6+4h)CY

t



Example: 2-input NAND

 Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates.

h copies

6C 2 2C

2 2 2

4hC B

A

x

Y

R Y

^{t }  ^{6 4  h RC} 

Rising time: nMOS - “off”

pMOS - “on”

Example: 2-input NAND

 Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates.

h copies

6C 2 2C

2 2 2

4hC B

A

x

Y

Example: 2-input NAND

 Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates.

h copies

6C 2 2C

2 2 2

4hC B

A

x

Y

t 

x R/2 Y

Consider that the nMOS resistance = (pMOS resistance)/2 = R/2

Example: 2-input NAND

 Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates.

h copies

6C 2 2C

2 2 2

4hC B

A

x

Y

       

 

2 2 2

2 6 4

7 4

R R R

t

C h C

h RC

       

 

(6+4h)C R/2 2C

x R/2 Y

Delay Components

 Delay has two parts – Parasitic delay

• 6 or 7 RC

• Independent of load – Effort delay

• 4h RC

• Proportional to load capacitance

Contamination Delay

 Best-case (contamination) delay can be substantially less than propagation delay.

 Ex: If both inputs fall simultaneously

6C 2 2C

2 2 2

4hC B

A

x

Y

R

(6+4h)CRY

 ^{3 2} 

t

  h RC

3 7C 2 2

2 2C

2C

Isolated Contacted Diffusion Merged

Uncontacted Shared Contacted Diffusion

Diffusion Capacitance

 we assumed contacted diffusion on every source/drain

 Good layout minimizes diffusion area

 Ex: NAND3 layout shares one diffusion contact – Reduces output capacitance by 2C

– Merged uncontacted diffusion might help too

Capacitance = 2C+2C+3C = 7C

Layout Comparison

 Which layout is better?

V_DD A

GND

B

Y

V_DD A

GND

B

Y