Top PDF Design of a High Speed Multiplier (Ancient Vedic Mathematics Approach)

Design of a High Speed Multiplier (Ancient Vedic Mathematics Approach)

Design of a High Speed Multiplier (Ancient Vedic Mathematics Approach)

Veda, by definition, is ‗knowledge‘. The Vedic Math has a much ancient origin though attributed to the techniques rediscovered between 1911-1918, by Sri Bharati Krshna Tirthaji Maharaja. Vedic mathematics is the ancient system of mathematics, or, precisely, it is a distinct technique of calculations based on simple rules and principles with which any mathematical problem can be solved, whether it may be arithmetic, algebra, geometry, trigonometry or even calculus. The Vedic mathematics is a coherent collective combination of 16 Sutras(Formulae) and 16 Sub-Sutras(the corollaries of the formulae). According to a theory, ―The sutras of Vedic Mathematics are the software for the cosmic computer that runs this universe.‖
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DESIGN OF 8-4 AND 9-4 COMPRESSORS FORHIGH SPEED MULTIPLICATION

DESIGN OF 8-4 AND 9-4 COMPRESSORS FORHIGH SPEED MULTIPLICATION

2010) and (Veeramachaneni et al., 2007). In high speed multiplier, 4-2 compressors have been widely used to lower the latency of the partial product reduction stages. Most of the commercial designs in the various processors in the market use 4 to 2 compressor. Even the number of partial product reduction stages cannot be reduced as much using the lower order compressors. Hence the delay of multipliers also was not reduced as much. The higher order compressors (5-3, 6-3 and 7-3) were used to improve the performance of multipliers earlier (Dandapat et al., 2010; Dadda, 1976). They have merged binary counter property into the high order compressors which have further reduced the partial product stages and power consumption. In this study, we have used 7-3 compressor which is designed by four full adders (Dadda, 1996) to improve the performance of multiplier. In this study, we have proposed 8-4 and 9-4 compressors which have further reduced the number of partial product stages of multipliers as compared to existing compressors. Moreover, the proposed compressors use less number of gates, so overall design area decreases. This technique offers less delay, but Energy Delay Product (EDP) is slightly higher than lower order compressor.
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High speed multiplier design using Decomposition Logic

High speed multiplier design using Decomposition Logic

Dadda generalized and extended Wallace’s results by noting that a full adder can be thought of as a circuit which counts the number of ones in the input, and then outputs that number in 2-bit binary form [4]. Using such a counter, Dadda postulated that, at each stage, only minimum amount of reduction should be done in order to reduce the partial product matrix by a factor of 1.5. In the Wallace method, the partial products are reduced as soon as possible. In contrast, Dadda’s method does the minimum reduction necessary at each level to perform the reduction in the same number of levels as required by the Wallace method resulting in a design with fewer full adders and half adders. The disadvantage of Dadda’s method is that it requires a slightly wider, fast CPA and has a less regular structure than Wallace’s. Fig. 1 shows an 8×8 multiplier designed using Dadda’s method.
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Design of Low Power Column Bypass Multiplier using FPGA and Implementation Using FIR Filter

Design of Low Power Column Bypass Multiplier using FPGA and Implementation Using FIR Filter

This design is advantageous than the previous two methods because, this design need not of connecting an extra bypassing circuitry since we are taking multiplicand bits instead of multiplier bits, and also with the help of BOOTH recoding unit we can definitely have at least one ‘0’ in the multiplicand. If multiplicand contains more zeros, higher power reduction can be achieved. Instead of bypassing rows of full adders, we propose a multiplier design in which columns of adders are bypassed. There is two advantages of this approach. First, it eliminates an extra correcting circuit needed; second, the modified Half Adder and Full Adder are simpler than that are used in the row-bypassing multiplier. Consider the multiplication shown in below figure, which executes 1010×1111. Here, in the first and third diagonals (enclosed by dashed lines), two out of the three input bits are 0: the “carry” bit from its upper right FA, and the partial product aibj (note that a0 = a2 = 0). As a result, the output carry bit of the FA is 0, and the output sum bit is simply equal to the third bit, which is the “sum” output of its upper FA. In this approach we propose Booth Recoding Unit will force multiplicand to have number of zeros, if does not have a single zero. The advantage here is that if multiplicand contains more successive number of one’s then booth- recoding unit converts these ones in zeros. More the number of zero’s more the power reduction can possible with high executing speed. Example for column bypassing:
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A Comparative Study on LUT and Accumulator Radix-4 Based Multichannel RNS FIR Filter Architectures

A Comparative Study on LUT and Accumulator Radix-4 Based Multichannel RNS FIR Filter Architectures

The direct implementation of N-tap FIR filter requires N MAC operations, which are expensive to implement in hardware due to its logic complexity and area requirement. Memory based structures are well-suited for the implementation of many digital signal processing (DSP) algorithms, which involve multiplication with a fixed set of coefficients. There are two basic variants of memory based techniques. One of them is based on distributed arithmetic (DA) for inner- product computation and the other is based on the computation of multiplication by look-up-table (LUT). In the LUT-multiplier-based approach [4], multiplications of input values with a fixed co-efficients are performed by a LUT consisting of all possible pre-computed product values corresponding to all possible values of input while in the DA based approach, LUT is used to store all possible values of inner-products of a fixed N –point bit-vector. If the inner-products are implemented in a straight- forward way, the memory-size of LUT multiplier based implementation increases exponentially with the word- length of input values, while that of the DA based approach increases exponentially with the inner-product- length. Attempts have been made to reduce the memory space in DA-based architectures using offset binary coding (OBC) and group distributed technique [17] .A decomposition scheme [16] is one of the techniques used for reducing the memory size of DA based implementation of FIR filter. But, it is observed that the reduction of memory size achieved by such decompositions is accompanied by the increase in latency as well as the increase in the number of adders and latches. In this paper proposed two new multichannel FIR filter architectures wherein the speed of operation increases or complexity of hardware reduces. Hardware complexity is reduced by manipulating the odd multiples of the fixed coefficient in the LUT design[4], whereas the speed of operation is increased by reducing the partial products required for accumulator based radix-4 multiplier[18] .
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VLSI IMPLEMENTATION OF AN ANALOG MULTIPLIER FOR MODEM

VLSI IMPLEMENTATION OF AN ANALOG MULTIPLIER FOR MODEM

In this paper “Low Voltage, Low Power, High Speed and High Linearity-CMOS Analog Multiplier for Modem is proposed”. The multiplier circuit is implemented in 180nm technology with minimum transistor sizes (W/L=180nm/180nm). It can be operated even at low Supply voltage VDD=0.5V. Band width of operation is about 4THz, which is suitable for high frequency/high speed applications

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Modified design for Full Swing SERF and High Speed SERF

Modified design for Full Swing SERF and High Speed SERF

Low-voltage performance of FS-SERF and HS-SERF The two proposed provide accurate logic levels at voltages as low as 0.3 Volts. In sub-threshold operation the power consumption reduces further at the cost of delay, as the sub threshold circuits are slow due to the dependence of operation on leakage currents only. The design can be operated at maximum frequency of 100MHz at 0.3 V. Increase speed can be achieved by increasing Vdd. The waveforms obtained from simulation of designs at 0.3V
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Design and Performance Analysis of Hybrid Adders for High Speed Arithmetic Circuit

Design and Performance Analysis of Hybrid Adders for High Speed Arithmetic Circuit

In Radhakrishnan Adder [5] a minimal transistor CMOS pass network XOR-XNOR cell that is fully compensated for threshold voltage drop in MOS transistors, is presented by the author. This new cell can reliably operate within certain bounds when the power supply voltage is reduced to certain level. It uses only six transistors for the combined XOR-XNOR cell and can operate reliably when the supply voltage is scaled down, as long as the voltage is not allowed to fall below double of threshold voltage. The total number of transistor used here for full adder operation is 14. The Design circuit is shown in figure 3.
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High Speed, Low Power Current Comparators with Hysteresis

High Speed, Low Power Current Comparators with Hysteresis

This paper, presents a novel idea for analog current comparison which compares input signal current and reference currents with high speed, low power and well controlled hysteresis. Proposed circuit is based on current mirror and voltage latching techniques which produces rail to rail output voltage as a result of current comparison. The same design can be extended to a simple current comparator without hysteresis (or very less hysteresis), where comparator gives high accuracy (less than 50nA) and speed at the cost of moderate power consumption. The comparators are designed optimally and studied at 180nm CMOS process technology for a supply voltage of 3V.
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Modeling of Multilayer Transmission Lines for High-Speed Digital Interconnects

Modeling of Multilayer Transmission Lines for High-Speed Digital Interconnects

The models are designed using electrostatic environment in order to compare our results with the other available methods. In the boundary condition of the model’s design, we use ground boundary which is zero potential ( V  0 ) for the shield. We use port condition for the conductors to force the potential or current to one or zero depending on the setting. Also, we use continuity boundary condition between the conductors and between the conductors and left and right grounds. The quasi-static models are computed in form of electromagnetic simulations using partial differential equations.
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Method of determining the speed of sheet washout for design of structures on slopes

Method of determining the speed of sheet washout for design of structures on slopes

It was noted that the study of the process of sheet washout should be made in condition of stability of inluencing factors: climate, topography, geology, soils, vegeta- tion and human activities. In order to validate the approach, the slopes of ravines in the Neskuchny Garden in Moscow were chosen. The selected slopes have similar climatic, geological, geomorphological, soil and phytological signs. This allows the authors to gather material for statistical analysis of the investigated process. In their experiment, the authors used lime trees and maples. Single measurement was made on elms and oaks. As an example, the authors present the results of measurements on site 1, locat- ed on the right side of the ravine Neskuchny Garden. A fairly high correlation coeficient (K=0.91) indicates strong linear relationship of lushing depth and the tree diameter and proves the validity of this method for approximate calculation of the depth of sheet washout.
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Study and Performance Analysis of High Frequency and High Speed Operational Amplifier

Study and Performance Analysis of High Frequency and High Speed Operational Amplifier

Abstract – The performance analysis of the two stage CMOS operational amplifiers employing Miller capacitor in conjunction with the common gate current buffer is presented. Unlike the previously reported design strategies of the opamp of this type, this results in the opamp with a lower power supply requirements, better phase margin and better speed. The Opamp is designed to exhibit a unity gain frequency of 1.46GHz and exhibits a gain of 115dB with a 117˚ phase margin. The slew rate is found as high as 50 V/µs. Power supply noise rejection is also better in case of current buffer compensation. As compared to the conventional approach, the current buffer compensation method results in a higher unity gain frequency hence higher bandwidth under the same load condition. Simulation has been carried out in LT-SPICE.
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Simulation of 64-bit MAC Unit using Kogge Stone Adder and Ancient Indian Mathematics

Simulation of 64-bit MAC Unit using Kogge Stone Adder and Ancient Indian Mathematics

In this section, the result of the Kogge stone adder, Vedic multiplier and MAC unit are displayed using VIRTEX-4 family, XC4VFX140 device, 11FF1517 package, -11 speed. Design summary of 64-bit MAC unit is displayed in Fig 5 (a), it contains the number and percentage of slices, LUT’s, IOB’s and CLK’s used by the unit, simulation output of 64-bit MAC unit is displayed in Fig 5 (b) and RTL view of 64-bit MAC unit is shown in Fig 5 (c):

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The Influence of Damping on Vibration Induced by High-Speed Trains

The Influence of Damping on Vibration Induced by High-Speed Trains

Although, slab-track solutions may offer certain advantages to the traditional ballasted tracks, in Portugal only ballasted lines are present and therefore this study is solely concerned with them. In this paper, full 3D model for a case study is constructed in a parametric way. Analyses performed by ANSYS and LS-DYNA are compared, [4]. Viability of 2D models is discussed, either as a longitudinal cut or as a transversal cut of the thee-dimensional model. For this purpose, full transient analyses are performed. Two types of damping, specified above, are examined. New materials are suggested in order to decouple efficiently rail and soil vibrations. Implementation of Rayleigh damping of soils is commented. Capabilities and limitations of numerical simulations are highlighted. In conclusion, this work contributes to a better understanding of surrounding soil vibrations, permitting better control of the train velocity and optimization of track design. Some developments make part of research project “Response of system railway track-soil to loads imposed by high speed trains” POCI/ECM/61114/2004, founded by Portuguese supporting research entity (Fundação para a Ciência e a Tecnologia).
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High Speed Area Efficient 8-point FFT using Vedic Multiplier

High Speed Area Efficient 8-point FFT using Vedic Multiplier

The goal of DSP is usually to measure, filter and/or compress continuous real-world analog signals. The first step is usually to convert the signal from an analog to a digital form, by sampling and then digitizing it using an analog-to-digital converter (ADC), which turns the analog signal into a stream of numbers. However, often, the required output signal is another analog output signal, which requires a digital-to-analog converter (DAC). Even if this process is more complex than analog processing and has a discrete value range, the application of computational power to digital signal processing allows for many advantages over analog processing in many applications, such as error detection and correction in transmission as well as data compression. DSP algorithms have long been run on standard computers, as well as on specialized processors called digital signal processor and on purpose-built hardware such as application-specific integrated circuit (ASICs). Today there are additional technologies used for digital signal processing including more powerful general purpose microprocessors, field-programmable gate arrays (FPGAs), digital signal controllers (mostly for industrial apps such as motor control), and stream processors, among others [2-3]. The FFT is one of the most commonly used digital signal processing algorithm. Recently, FFT processor has been widely used in digital signal processing field applied for OFDM, MIMO-OFDM communication systems. FFT/IFFT processors are key components for an orthogonal frequency division multiplexing (OFDM) based wireless IEEE 802.16 broadband
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An Area Efficient and High Speed Reversible Multiplier Using NS Gate

An Area Efficient and High Speed Reversible Multiplier Using NS Gate

In digital co mputer system a major p roble m has been found that the Power dissipation which leads to bring some research on the methods to decrease this Area efficient, high speed. This is the main cause to give birth to reversible computing systems for digital computers and designs. Reversible computing is the path to future computing technologies, which all happen to use reversible logic. In addition, reversible computing will become mandatory because of the necessity to decrease power consumption. Reversible logic c ircuits have the same number of inputs and outputs, and have one-to-one mapping between vectors of inputs and outputs; thus the vector of input states can be always reconstructed from the vector of output states . Consequently, a computation is reversible, if it is always possible to uniquely recover the input, given the output. Each gate can be made reversible by adding some additional input and output wires if necessary. The main aim of th is reversible computing is to lower the power dissipation, area efficient and high speed and some other advantages like security of data and prevention of errors etc... Reversible logic has so ma ny applications low power CMOS, nanotechnology, DNA computing and quantum computing. There are two primary design imp le mentations in this study which are the major spotlights. The first one is reversible design gate and the second one is multiplier design using reversible gates. In this manuscript we have imp le mented a 8 * 8 reversible design called “NSG(Non linear Sign Flip)”. The total project is implemented in Xilinx 14.7 ISE with Spartan 3E family. Keywords: Lo w Po wer Consumption, Reversibility, NSG, Constant Input, Garbage Output, ALU.
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A new high speed low power performance of 8- bit parallel multiplier-accumulator using modified radix-2 booth encoded algorithm

A new high speed low power performance of 8- bit parallel multiplier-accumulator using modified radix-2 booth encoded algorithm

1) Basic Concept: If an operation to multiply two –bit numbers and accumulate into a 2 -bit number is considered ,the critical path is determined by the 2 - bit accumulation operation. If a pipeline scheme is applied for each step in the standard design of Fig. 1, the delay of the last accumulator must be reduced in order to improve the performance of the MAC. The overall performance of the proposed MAC is improved by eliminating the accumulator itself by combining it with the CSA function. If the accumulator has been eliminated, the critical path is then determined by the final adder in the multiplier. basic method to improve the performance of the final adder is to decrease the number of input bits. In order to reduce this number of input bits, the multiple partial products are compressed into a sum and a carry by CSA. The number of bits of sums and carries to be transferred to the final adder is reduced by adding the lower bits of sums and carries in advance within the range in which the overall performance will not be degraded.
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Power Aware & High Speed Booth Multiplier based on Adiabatic Logic

Power Aware & High Speed Booth Multiplier based on Adiabatic Logic

Adiabatic circuits are a particularly attractive approach by recycling energy of node capacitance to reduce power dissipation, which would be dissipated as heat in the conventional CMOS. Several adiabatic logic architectures, such as ECRL (Efficient Charge Recovery Logic), SCAL (Source Coupled Adiabatic Logic) and DTGAL (Dual Transmission Gate Adiabatic Logic) etc, have been reported and achieved considerable energy saving.

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Design of High speed Low Power Reversible Vedic multiplier and  Reversible Divider

Design of High speed Low Power Reversible Vedic multiplier and Reversible Divider

Vedic mathematics is the ancient Indian system of mathematics which mainly deals with Vedic mathematical formulae and their application to various branches of mathematics. Vedic mathematics was reconstructed from the ancient Indian scriptures (Vedas) by Sri Bharati Krisna Tirtha after his research on Vedas [16]. He constructed 16 sutras and 16 upa sutras after extensive research in Atharva Veda. The most famous among these 16 are Nikhilam Sutram, Urdhva Tiryakbhayam, and Anurupye. It has been found that Urdhva Tiryakabhayam is the most efficient among these. The beauty of Vedic mathematics lies in the fact that it reduces otherwise cumbersome looking calculations in conventional mathematics to very simple ones. Reversible logic is one of the promising fjelds for future low power design technologies. Since one of the requirements of all DSP processors and other hand held devices is to minimize power dissipation multipliers with high speed and lower dissipations are critical. This paper proposes an implementation of Reversible Urdhva Tiryakabhayam Multiplier which consists of two cardinal features. One is the fast multiplication feature derived from Vedic algorithm Urdhva Tiryakabhayam and another is the reduced heat dissipation by the virtue of implementing the circuit using reversible logic gates. Also we propose a new reversible division circuit. This proposed divider is unsigned division hardware. Our proposed reversible divider composed of reversible components like reversible multiplexer, reversible PIPO left-shift register, reversible register, reversible register with
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HIGH SPEED BUTTERFLY ARCHITECTURE FOR CIRCULAR CONVOLUTION USING FNT WITH PARTIAL PRODUCT MULTIPLIER

HIGH SPEED BUTTERFLY ARCHITECTURE FOR CIRCULAR CONVOLUTION USING FNT WITH PARTIAL PRODUCT MULTIPLIER

The result obtained at the final-stage of BOWA is given at the input of a modulo 2 n + 1 adder in order to accept these two summands and produce the required product in the diminished-1representation.In the proposed butterfly architecture for circular convolution based on FNT, the BO can accept four operands in the diminished-1 number system. Every point wise multiplication only needs to produce two partial products rather than one product. The operation can be accomplished by taking away the final modulo 2 n +1 adder of two partial products in the multiplier. Thus the final modulo 2 n +1 adder is omitted and the modulo 2 n +1 partial product multiplier is employed to save the delay and the area.
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